| IBM and Motorola are ahead of schedule with the
development of their PowerPC 601, the first in a series of
RISC microprocessors on which IBM and Apple will base
their next generation of personal computers. The
first-pass silicon was ready last October, less than a
year after a joint team began work in Austin, Texas. If development continues apace, IBM and Apple expect to introduce their first PowerPC systems by late 1993. The 601-based systems will be relatively inexpensive and will rival the performance of low-end workstations. As reported last month in Microbytes, future chips in the PowerPC family will include the 603, for portable systems; the 604, for mainstream desktop computers; and the 620, for high-end systems and servers. The 601 is a streamlined derivative of the single-chip RISC engine found in IBM's RISC System/6000 Model 220 workstation. Evolutionary rather than revolutionary, the 601 combines the basic architecture of the RS/6000 with an enhanced version of the bus interface from Motorola's 88110 RISC processor. Even though the 601 improves on the RS/6000's architecture, it's considerably less integrated than the single-chip RS/6000. Gone are on-chip controllers for DMA, interrupts, and memory, along with some automatic timers. IBM says it has scaled down the integration to keep the 601 from becoming too system-specific — an important design goal for a CPU that's intended to be used in machines from IBM, Apple, Groupe Bull, Thomson-CSF, and others. The superscalar architecture of the 601 has three execution units that separately handle integer operations, floating-point operations, and branches. By routing these types of instructions to the appropriate pipelines, the chip can dispatch up to 3 instructions per cycle. The branch pipeline has two stages, and the integer pipeline has four. The six-stage floating-point pipe-line is tuned for single-precision math, and double-precision operations are double-pumped through the pipeline's two execution stages. Most integer instructions execute in only 1 cycle, thanks to hardware support for multiply, divide, and other special operations. The FPU achieves 1- or 2-cycle throughput, depending on the type of operation and the level of precision. The chip includes a 32-KB data/instruction cache, an MMU (memory management unit) with 52-bit virtual addressing, and support for symmetric multiprocessing. Using 0.6-micron static CMOS technology, it packs 2.8 million transistors into a 304-pin package less than 11 mm square. It operates at 3.6 V and consumes 9 W at 50 MHz. Performance benchmarks aren't available, but IBM offers the following "conservative estimates based on simulations.": SPEC Integer '89 benchmark: 40 at 50 MHz, 50 at 66 MHz; SPEC Floating-Point '89 benchmark: 60 at 50 MHz, 80 at 66 MHz. That's more than twice as fast as the RS/6000 Model 220 chip, which runs at 33 MHz. IBM says the PowerPC 601 will be "aggressively priced." The chip could cost as little as $50. Systems could sell for $1000 to $2000. Copyright 1994-1997 BYTE |