Marvell’s new Armada 1500 media processor supersedes an Intel x86 chip in the second-generation Google TV reference platform—a switch that would be bigger news if Google TV were popular and if Intel hadn’t already retreated from this market. Nevertheless, the design win helps establish Armada as an up-and-coming product line for smart TVs, Blu-ray players, and advanced set-top boxes. Although Intel's Atom CE4100 (“Sodaville”) processor delivers sufficient performance and has all the required I/O interfaces, it’s a first-generation 45nm Atom SoC that burns more power and almost certainly costs more. Last October, Intel closed its smart-TV Digital Home Group to refocus on set-top boxes and Internet gateways, leaving a small vacuum for an ARM ally to fill. [January 30, 2012]

With a bumper crop of innovations to choose from, deciding which new microprocessor-related technology best deserves our Analysts’ Choice Award wasn’t easy. Our pick for 2011: the Hybrid Memory Cube, which stacks multiple DRAM chips inside a single package and connects the die using through-silicon vias (TSVs). Although engineers have been working for years on the concept of three-dimensional ICs, new developments in 2011 virtually guarantee that stacked-memory devices are finally on their way to commercial production in the near future. Other technologies we considered for this award are noteworthy, too. We nominated four candidates from Intel: tri-gate (FinFET) transistors, near-threshold voltage (NTV) transistors, the Thunderbolt I/O interface, and AVX2 extensions. In addition, we considered SuVolta's PowerShrink technology and the merged CPU-DRAM architecture of Venray's Tomi Borealis processor. [January 23, 2012]

• Figure 1: Hybrid Memory Cube. The first commercial devices will stack four DRAM die connected using through-silicon vias.

Freescale has its own twist on ARM's recently announced "Big.Little" strategy. Early next year, Freescale will introduce a new family of 32-bit processors that have ARM Cortex-A5 cores and a Cortex-M4 core. This asymmetric or heterogeneous multicore design combines the high performance of application processors with the real-time response of microcontrollers. The new products have no brand name yet, so Freescale refers to them as asymmetric embedded MPUs (AeMPUs). This family will fit between Freescale's existing Kinetis 32-bit MCUs and i.MX 32-bit SoCs, all of which also use ARM CPUs. The new chips can be considered application-class SoCs with real-time credentials or 32-bit MCUs with application aspirations. By contrast, ARM’s Big.Little strategy integrates a Cortex-A15 ("big") core with a Cortex-A7 ("little") core and is designed to save power in mobile application processors. [December 5, 2011]

• Figure 1: Freescale AeMPU simplified block diagram.

Embedded SoCs are growing so powerful that they resemble last year's smartphone application processors. In fact, they probably are derived from last year's smartphone processors. Texas Instruments' new Sitara AM335x chips integrate an ARM Cortex-A8 core with Neon SIMD extensions, 3D graphics, a display controller, a touchscreen controller, Gigabit Ethernet, USB, cryptography acceleration, and numerous on-chip peripherals—much like TI's own OMAP3. TI has announced six basic AM335x chips at speed grades of 275-720MHz. Volume pricing ranges from $4.99 to $14.99, and target applications include industrial automation, consumer medical devices, printers, networked vending machines, portable navigators, and consumer electronics. [November 14, 2011]

If Altera buys a toothpaste factory, Xilinx will invest in mouthwash. And if Xilinx prepares to send a man to Mars, Altera will start building rockets. The two leading FPGA vendors are that competitive. So it's no surprise that Altera has announced its answer to Xilinx's Zynq chips, which are customizable SoCs that integrate ARM Cortex-A9 cores and hard peripherals with programmable logic. Altera's new Cyclone V and Arria V "SoC FPGAs" also integrate ARM Cortex-A9 cores and hard peripherals with programmable logic. But Altera isn't a copycat, because both companies are hearing the same pleas from customers and are building on experience with similar products introduced more than a decade ago. [October 31, 2011]

• Figure 1: Altera SoC FPGA block diagram.

• Figure 2: Replacing discrete chips with an Altera SoC FPGA.

• Table 1: Altera's Cyclone V and Arria V SoC FPGAs.

• Table 2: Comparing Altera's SoC FPGAs with Xilinx's Zynq processors.

NetLogic is forging ahead with its next-generation XLP II family of networking processors, even while Broadcom's pending acquisition of the company moves toward resolution. To keep the heat on rivals like Cavium, Freescale, and Intel, NetLogic must keep its transition to a new product line and 28nm technology on schedule. At the Linley Tech Processor Conference in San Jose last week, NetLogic disclosed new information about the XLP II family. The first member is the eight-core XLP332E, which is scheduled to sample in 1Q12. The XLP332E will introduce the EG4400 CPU core, an enhanced version of the MIPS64-compatible EC4400 core found in today's XLP-family processors. The XLP332E will also introduce PCI Express 3.0 and USB 3.0 to NetLogic’s product line. [October 10, 2011]

• Figure 1: NetLogic XLP332E block diagram.

• Figure 2: NetLogic's Interchip Coherency Interface supports four- and eight-chip memory-coherent clusters.

• Table 1: Comparison of selected XLP and XLP II processors: the XLP332E, XLP316L, XLP964, XLP980, and XLP832.

At the recent Embedded Systems Conference in Boston, STMicroelectronics unveiled the world's fastest MCUs based on ARM's Cortex-M4F. Although there are faster 32-bit MCUs, the 168MHz STM32 F4 chips outrun all others that use ARM's popular digital-signal controller CPU. The STM32 F4 series includes four basic designs with various integrated peripherals. All the chips have a Cortex-M4F with ARM's digital-signal extensions and optional 32-bit FPU. ARM introduced this core last year as its first digital-signal controller (DSC), but it's actually a Cortex-family upgrade from the popular ARM9 and ARM11. [October 10, 2011]

Intel Labs is experimenting with microprocessors that save energy by running transistors at very low voltages near their threshold between on and off states. Prototype chips are promising enough that commercial products may be only a few years away. If Intel can overcome the reliability and manufacturing challenges, microprocessors using this technology will come close to achieving their maximum theoretical power-performance efficiency. Intel disclosed the near-threshold voltage (NTV) project at the recent Intel Developers' Forum in San Francisco. The concept isn't new—academic research into near-threshold and subthreshold semiconductors stretches back 30 years. In 1972, researchers theorized that the lowest possible operating voltage for a CMOS circuit is 36mV, which some experiments have approached. At levels near the threshold voltage between on and off states, the circuit consumes only about 10% of the energy it uses when operating at its nominal voltage. [October 3, 2011]

Frustrated by diminishing returns from processors with more than eight CPU cores, a Chinese research team has designed a 64-core processor to explore various paths toward higher performance. Although the experimental design exploits both instruction-level and data-level parallelism, the key to good performance scaling appears to be fine-grained thread-level parallelism. This design requires programmers to explicitly create threads, but a dynamic thread manager supervises their execution, allowing a program to spawn more threads than the processor can execute at once. To reduce the overhead of managing so many threads, the processor needs a hardware-accelerated synchronizer that eliminates deadlocks. Those are some early results of the Godson-T research project, a government-funded endeavor at the Institute of Computing Technology (Chinese Academy of Sciences) in Beijing. [September 19, 2011]

• Figure 1: Godson-T CPU-level block diagram.

• Figure 2: Godson-T chip-level block diagram.

• Figure 3: Godson-T simulation benchmark results.

The next major extension of the world's most complex instruction-set architecture is coming in 2013 with a new Intel processor code-named Haswell. This processor will add hundreds of new instructions, including a set called Advanced Vector Extensions 2. AVX2 follows this year's debut of AVX in "Sandy Bridge" PC processors and AMD processors with the new Bulldozer CPU. Also coming in Haswell are 96 fused multiply-add (FMA) instructions with a new three-operand format (FMA3), plus 16 new general-purpose instructions. All together, these "Haswell new instructions," as Intel calls them, herald the biggest x86-architecture expansion in years. And even before Haswell, Intel will introduce seven new instructions with a processor code-named Ivy Bridge in 2012. [August 29, 2011]

• Table 1: Summary of Intel's recent and future x86 extensions.

• Table 2: Ivy Bridge new instructions.

• Table 3: New or improved instructions in Advanced Vector Extensions 2 (AVX2).

• Table 4: Haswell's new FMA instructions.

• Table 5: Haswell's new general-purpose instructions.

Intel has demonstrated early hardware and software developed for its evolving manycore processors, which aim to expand the x86 architecture's dominance in supercomputers and high-performance computing. At the recent International Supercomputing Conference in Germany, Intel demonstrated software developed by partners using a Many Integrated Core (MIC, pronounced "mike") processor salvaged from the ill-fated Larrabee GPU project. Those partners include CERN (Switzerland), the Korea Institute of Science and Technology Information, and the Leibniz Supercomputing Centre (Germany). Colfax, Dell, Hewlett-Packard, IBM, SGI, and Supermicro showed prototype MIC servers and workstations. The development processor, code-named Aubrey Isle, has 32 CPU cores. When the first commercial MIC processor enters production, it will have at least 50 CPUs. Most customers will buy it as a math coprocessor on a PCI Express board, which is code-named Knights Corner. [July 18, 2011]

• Figure: Aubrey Isle die photo with overlay.

Freescale has announced a whole new series of QorIQ-family processors that will deliver about four times the performance and twice the power efficiency of today's best P-series chips. Scheduled to begin sampling early next year, the AMP (Advanced Multiprocessing) series will debut with Freescale's first multithreaded CPU core, up to a dozen CPUs per chip, higher clock frequencies, faster offload engines, resurrected AltiVec extensions, and other goodies. The first T-series AMP processor will be the T4240, which will have 12 dual-threaded CPUs running at clock speeds of up to 2.0GHz—enough to sustain packet forwarding at 48Gbps in data-plane applications. For control-plane processing, future T5-series chips with six CPUs will aim for clock speeds as high as 2.5GHz. [June 27, 2011]

• Figure 1: Freescale QorIQ AMP T4240 block diagram.

• Table 1: Freescale's new QorIQ AMP family.

Emerging after five years in stealth mode, Silicon Valley startup SuVolta is promising to slash the dynamic power consumption of CMOS transistors by 50% and leakage current by 50% to 80% without sacrificing performance. The company says its PowerShrink technology requires only minor modifications to existing bulk-CMOS processes and adds little cost, beyond licensing. Although these claims naturally arouse skepticism, SuVolta has successfully produced SRAM test chips in 65nm and 28nm technology, and PowerShrink has been adopted by a major customer: Fujitsu. The Japanese chipmaker and foundry will use PowerShrink to manufacture ASICs, ASSPs, and SoCs in 65nm CMOS. [June 13, 2011]

Via Technologies has announced its first quad-core x86 processor—and it's also the world's lowest-power x86 processor sporting four CPUs. Although intended primarily for notebook PCs and entry-level desktops, the company's new Nano QuadCore processor may also find its way into high-performance embedded systems and power-efficient servers. Following a trend set by AMD and Intel, Via's first quad-core device combines two dual-core die in a single package. Each die is an 11mm × 6mm Nano X2, which Via announced in January. The 400-pin multichip package (NanoBGA2) is 21mm square, and it maintains pin compatibility with Nano X2 and several other Via processors: the Nano E Series, Eden, Eden X2, and C7. TSMC will manufacture Nano QuadCore in 40nm CMOS, with volume production scheduled for 3Q11. [May 30, 2011]

Cadillac introduced tailfins to evoke high-tech style in the 1950s, but Intel's new finned transistors are far from cosmetic. Purely functional, highly efficient, yet equally brash, these fin-shaped field-effect transistors (FinFETs) are sure to be copied as widely as Cadillac's useless appendages were—and they will play a similar role in defining an era. Intel refers to its FinFETs as tri-gate transistors and touts them as the first true three-dimensional devices built on planar integrated circuits. Don't confuse these "3D" transistors with 3D transistor stacking, an entirely different technology that builds transistors in multiple layers. Instead, a FinFET rises above the flat silicon substrate, creating a 3D gate structure that has much more volume than a planar gate while squeezing into approximately the same horizontal space. [May 23, 2011]

• Figure 1: Micrographs of planar transistors and Intel's FinFETs.

• Figure 2: Two illustrations of an Intel FinFET.

• Figure 3: Threshold-voltage (V_t) characteristics of FinFET and planar transistors.

• Figure 4: Gate-delay characteristics of FinFET and planar transistors.

As Altera promised last year, a new MIPS-compatible CPU core optimized for synthesis in programmable logic is now available. The MP32 core targets Altera's FPGAs, including the high-end Stratix-IV, midrange Arria-II, and low-end Cyclone-III. Although it's larger, more expensive, less configurable, and no faster than Altera's proprietary Nios II core, the MP32 supports the more popular MIPS32 architecture and runs Wind River's VxWorks real-time operating system (RTOS). System Level Solutions (SLS), an Altera partner based in Gujarat, India, will sell and support the MP32. SLS collaborated with Altera and MIPS Technologies on the core's development. [May 16, 2011]

At the recent Linley Tech Mobile Conference in San Jose, Kilopass announced the first nonvolatile embedded memory that is reprogrammable up to 1,024 times and is compatible with digital-IC processes in 40nm bulk CMOS. The company has also produced test chips in 28nm CMOS. Branded Itera, the new memory is licensed as intellectual property (IP) to chip designers. It's available now for 40nm processes at GlobalFoundries, TSMC, and UMC. It will be available for 55nm and 65nm processes in 3Q11 and for 28nm processes in 4Q11. Block sizes range from 32 bits to 1Mb, and write endurance ranges from 104 to 1,024 cycles. [May 9, 2011]

Not satisfied to have merely the most powerful CPU core in a network processor, NetLogic has doubled the number of CPUs in its highest-end XLP product. The new XLP864 has 16 of NetLogic's MIPS64-compatible EC4400 cores—twice as many CPUs as the company's previous top-shelf chip, the XLP832. Packet-throughput performance doubles to 80Gbps, easily outrunning other multicore embedded processors. The 64-bit XLP864 is designed primarily for data-plane processing in large routers, security appliances, storage subsystems, next-generation cellular networks, and other communications equipment. At its fastest target clock frequency of 2.0GHz, it can process 120 million packets per second. [April 25, 2011]

• Table 1: Key parameters for high-end network processors from Cavium, Freescale, and NetLogic.

Metal tools delivered humanity from the Stone Age, and now, metal is enabling another technological breakthrough. For the first time, metal-gate transistors are broadly available to chip designers, allowing them to create higher-performance microprocessors that can still occupy less silicon and consume less power. This nanoscale application of metallurgy has been touted as the biggest advance in electronics since the invention of planar integrated circuits. As usual, Intel got there first. In 2007, Intel introduced the first microprocessors built in its new 45nm high-k metal-gate (HKMG) process. The rest of the semiconductor industry has been waiting four years for the same technology. Now, at the 32/28nm node, the leading independent foundries are introducing their own HKMG processes, and their first 28nm HKMG chips are entering production this year. [April 18, 2011]

• Figure 1: Chip shrinkage, 90nm to 28nm.

• Figure 2: Transistor evolution, 250nm to 28nm.

• Figure 3: Intel's tri-gate transistor.

• Table 1: GlobalFoundries 32/28nm-process variations.

• Table 2: TSMC 28nm-process variations.

Some ideas never die, no matter what misfortunes they suffer in the marketplace. One such idea is embedding a hardened CPU core in a programmable logic device. Developers dream of a flexible off-the-shelf alternative to costly ASIC projects and relatively inflexible ASSPs, but a successful formula has thus far eluded FPGA market leaders Xilinx and Altera, as well as several short-lived startups. Now, Xilinx is trying again. On March 1, the company announced the first products in its Zynq Extensible Processing Platform, foreshadowed last year in a joint announcement with ARM. Initial Zynq processors integrate dual 800MHz ARM Cortex-A9 CPUs with 28,000 to 235,000 programmable logic cells, up to 1.86MB of block RAM, hundreds of DSP multipliers, 256KB of tightly coupled memory, on-chip peripherals, and up to 12 high-speed serial transceivers. [March 7, 2011]

• Figure 1: Zynq block diagram.

• Table 1: Comparison of the Zynq Z-7010, Z-7020, Z-7030, and Z-7040.

Texas Instruments (TI) has announced six DaVinci digital-media processors with faster video accelerators and higher integration, allowing a single chip to replace eight or more chips in some cases. All the new processors unite at least one HD-video accelerator with an ARM Cortex-A8 CPU core and a TI C674x-series DSP, aiming for higher-end video applications such as surveillance systems, multiscreen videoconferencing, professional broadcasting, digital signage, and medical imaging. Lower-power versions of the chips are also suitable for some consumer electronics. [March 7, 2011]

ARM is expanding its Cortex-R family of real-time embedded-processor cores with two new CPUs: Cortex-R5, an enhancement of Cortex-R4F, and Cortex-R7, an offspring of the powerful Cortex-A9. Both are designed for single- or dual-core implementations. Cortex-R7 is a radical departure from the norm: never before has an intellectual-property vendor offered such an advanced CPU design for real-time embedded applications. It's a dual-issue superscalar machine with an 11-stage integer pipeline, instruction reordering, speculative execution, and optional symmetric multiprocessing. For less demanding applications, ARM's Cortex-R5 improves on the four-year-old Cortex-R4F. [February 21, 2011]

• Figure 1: ARM Cortex-R7 block diagram.

• Figure 2: Dual ARM Cortex-R7 MPCore CPUs in an LTE baseband chain.

• Figure 3: Cortex-R7/Cortex-R5 pipeline diagram.

• Figure 4: Multicore coherence with Cortex-R5 and Cortex-R7.

• Table 1: Comparison of ARM's new Cortex-R5 and Cortex-R7 against competing CPUs.

Targeting networked storage systems, 3G/4G base stations, and security applications, NetLogic will sample three versions of its newest quad-core processor this quarter. The XLP316 has Serial ATA (SATA) interfaces, the XLP316L has serial RapidIO (sRIO), and the XLP316S has hardware acceleration for deep packet inspection. All are significant upgrades over previous chips in the XLR and XLS families. Although NetLogic disclosed basic information about the XLP316 during a large rollout of XLP processors last summer, the company didn't announce these variations at that time. (See MPR 7/26/10-01, "NetLogic Broadens XLP Family.") [February 14, 2011]

There was a time when licensable embedded-processor cores led a quiet existence in the shadows of desktop and server processors. No more. As smartphones, tablets, e-readers, and other mobile devices supersede PCs in the minds and pocketbooks of consumers, SoCs with licensable CPU architectures are emerging as the dominant species of microprocessor. This evolution is transforming the industry, and 2010–2011 may be the turning point. This year-end review article summarizes events in 2010 related to licensable embedded-processor cores and considers likely developments in 2011. The rise of tablet computers is a fresh opportunity for many companies, and Microsoft's plans to port Windows 8 to ARM will alter the CPU landscape. [January 17, 2011]

Today's high-performance microprocessors are mostly memory, not logic. Of the 774 million transistors in an Intel Core i7-860 processor, for example, about 69% are SRAM transistors in the 8MB L3 cache. Now, a Texas-based startup, Venray Technology, is bucking the trend toward bigger caches—and the march toward bigger CPUs, too. Instead of building expensive six-transistor (6T) or eight-transistor (8T) SRAM cells in a logic process to accommodate the processor, Venray is moving the processor to commodity-DRAM processes, whose 1T memory cells are cheaper to manufacture and less leaky. Merging the CPU with DRAM dramatically boosts memory bandwidth, reduces memory latency, and slashes power consumption by eliminating caches and shortening the CPU-memory interface. [December 27, 2010]

• Figure 1: Venray's Aurora test chip.

• Figure 2: Thread-Oriented MIcroprocessor (TOMI) block diagram.

• Figure 3: Block diagram of Venray's "Shirtbook" tablet.

Intel has introduced an interesting alternative to custom chips: an Atom CPU packaged with an Altera FPGA in a multichip module. The new Atom E600C series (previously known as Stellarton) is suitable for some low-volume embedded applications that need to wrap an x86 processor in application-specific logic. One die is an Atom E600-series single-core processor ("Tunnel Creek"), which has a 512KB L2 cache, an Intel GMA600 graphics engine, an Intel HD Audio engine, an LVDS display interface, a 32-bit DDR2-800 memory controller, four lanes of PCI Express, and miscellaneous I/O. The FPGA die is an Altera Arria II GX, which has 60,214 programmable logic elements, 312 DSP blocks, 5.2Mb of embedded memory, one PCIe hardware block, and eight 3.125Gbps transceivers. [December 13, 2010]

Tablet computers are the latest craze, making netbooks so...2009. So why are AMD's first integrated CPU/GPU Fusion chips intended mainly for netbooks? For one, Fusion processors for desktop PCs aren't ready yet. Wait until next year. Second, the new processors aren't only for netbooks. If OEM customers want to use these low-power processors to build large-screen notebooks or even desktop PCs, AMD is happy to sell them the chips, no strings attached. And third, despite the hype over smartphones and tablets, netbooks remain a profitable market segment in which AMD has no presence whatsoever. If the struggling company can capture its usual 10% to 20% of the market, its share will be infinitely better than it is now. [December 6, 2010]

• Figure 1: AMD Fusion block diagram.

• Figure 2: AMD Ontario / Zacate die photo.

• Figure 3: Brazos system-architecture diagram.

• Figure 4: Power consumption for AMD's Brazos platform versus Intel's Pine Trail platforms.

• Table 1: AMD's first Fusion processors.

• Sidebar 1: AMD's Blurry Vision
  • Figure: AMD's "Vision" labels and matching PC applications.

  • Figure: "Vision" labels aligned with AMD's 2011 PC platforms.

• Sidebar 2: AMD & Intel Code-Name Glossary

Freescale's newest QorIQ communications processors expand the low-end P1 series with four chips that supersede older PowerQuicc models, upgrading the CPU from the Power e300 to the Power e500v2 core. Clock speeds of the new P1010/P1010E and P1014/P1014E will range from 533MHz to 800MHz while holding maximum power consumption to 2.75W. Target applications include small-business routers, network-attached storage (NAS) controllers, digital-video surveillance systems, and industrial control-area networks. [November 29, 2010]

Chips are breeding faster than rabbits at Cavium, the rapidly growing supplier of networking and security processors. Today, Cavium announced four new series in the 64-bit Octeon II family, populating a product line that now spans an unprecedented range from 1 to 32 CPU cores per chip. The new Octeon II series are the CN60xx, CN61xx, CN62xx, and CN66xx. They join the CN63xx, CN67xx, and CN68xx series announced earlier this year. The new brood fills the low-end to midrange Octeon II line, leaving no significant gaps. Family members differ in their number of CPUs, clock speeds, L2 caches, memory controllers, networking accelerators, packet interfaces, and other I/O. [November 15, 2010]

• Figure 1: Cavium's Octeon II family.

• Figure 2: Power savings with Octeon II's PowerOptimizer.

• Figure 3: Cavium Octeon II CN66xx block diagram.

• Table 1: Key parameters for Cavium's Octeon II family.

• Table 2: Comparison of midrange networking processors.

• Table 3: Comparison of low-end networking processors.

Embedding a CPU core and peripherals in an FPGA is the fastest way to rush an SoC to market, but the disadvantages have kept most developers loyal to conventional fixed logic. Now, Altera is again using embedded CPUs as bait to lure the industry toward reconfigurable logic. This time, the world's second-largest FPGA company is pitching three different CPU architectures—ARM, MIPS, and Nios II—plus a fourth option of the x86 in a multichip module from Intel. These choices span a broader range of implementation options than ever before. Developers will be able to choose a hard core (the foundry builds the CPU in fixed logic on the same die as the programmable fabric), soft cores (developers compile a synthesizable CPU for the fabric at design time), and the Intel multichip module (which pairs an Atom processor with an Altera FPGA). Although Altera and other FPGA vendors have offered both hard and soft CPUs for years, Altera's new "Embedded Initiative" is the most comprehensive CPU-FPGA strategy to date. [October 25, 2010]

• Figure 1: Altera's options for implementing SoCs in FPGAs.

MIPS Technologies is fighting to defend its strong market positions in home consumer electronics and networking while trying to win new ground in mobile electronics. To accomplish these objectives, the company needs increasingly powerful processors that reduce power consumption—the same conflicting design goals that bedevil almost all of today's CPU vendors. At the recent Linley Tech Processor Conference in San Jose, MIPS introduced its most powerful embedded-processor core to date: the MIPS32 1074K. Designed primarily for multicore SoCs with two to four CPUs, the 32-bit 1074K combines the strong single-thread performance of the MIPS32 74K with the cache-coherent multiprocessing of the MIPS32 1004K. The licensable 1074K is a fully synthesizable core, is portable to any foundry, and is available now. [October 11, 2010]

• Figure 1: High-performance MIPS32 licensable CPU cores.

• Figure 2: MIPS32 1074K pipeline diagram.

• Figure 3: MIPS Coherent Processing System (CPS).

• Table 1: MIPS32 1074Kf specifications in TSMC's 40nm-G process.

• Table 2: Comparison of the MIPS32 1074K/1074Kf with the MIPS32 1004K/1004Kf, IBM PowerPC 476FP, and ARM Cortex-A9 MPCore. All are high-performance licensable 32-bit CPUs with cache-coherent SMP.

Aiming to build the world's fastest supercomputer using domestic technology, the Chinese Academy of Sciences is boosting the performance of its home-grown Godson microprocessors with powerful vector-processing units, new SIMD instructions, additional CPU cores, and a leap to 28nm technology. Within a few years, the Chinese hope, an all-native machine will rule the Top 500 list of the world's biggest iron. Three new Godson chips are in development. Godson-3C will be the fastest new member of the family, as well as the most sophisticated Chinese microprocessor yet disclosed. Scheduled for production in 2012, it will be manufactured in a 28nm process and will have 16 CPU cores—twice as many as Godson-3B, another new processor, which achieved first silicon in a 65nm process this month. A third new chip, Godson-2H, is a smaller single-core design with integrated GPU, memory controller, and peripheral controllers. Intended for low-cost PCs, netbooks, and embedded systems, Godson-2H will also be manufactured in 65nm and is slated for production in 2H11. [September 27, 2010]

• Figure 1: Milestones of Godson evolution.

• Figure 2: Godson GS464V block diagram.

• Figure 3: Godson's memory-access coprocessor.

• Figure 4: Godson-3B layout.

• Figure 5: Godson-2H block diagram.

Freescale is adding packet-acceleration hardware to the QorIQ P1 and P2 series, matching a feature previously available only in the higher-priced P3, P4, and P5 series. At the same time, Freescale announced a new series of PowerQuicc II Pro chips, reassuring customers that the older PowerQuicc family lives on. The new QorIQ chips are the single-core P1017, dual-core P1023, and quad-core P2040. All have Freescale's Data-Path Acceleration Architecture (DPAA)—a fancy name for the packet-acceleration hardware that first appeared in the eight-core P4080, Freescale's largest networking chip. Extending DPAA to the lower-priced chips allows software developers to use the same code, tools, drivers, frameworks, and application programming interfaces (APIs) across the whole QorIQ family. [September 6, 2010]

• Figure 1: Freescale QorIQ P2040 block diagram.

• Table 1: New processors in Freescale's QorIQ family.

• Table 2: Comparing Freescale's P2040 with Cavium and NetLogic competitors.

• Table 3: Key parameters for the new PowerQuicc MPC830x processors.

For two years, Intel's Atom processors have utterly dominated the low-power x86 market, winning designs in the vast majority of netbooks while gaining market share in other segments as well. Atom has almost totally eclipsed Via Technologies' Centaur processors, which pioneered the concept of a smaller and simpler x86. Meanwhile, AMD has been virtually AWOL. Athlon Neo runs much hotter than Atom, and AMD's other x86 processors are optimized for high performance in servers, desktops, and mainstream notebooks. Now, AMD is clawing back. Its newest CPU core, code-named Bobcat, should beat Atom in single-thread performance at similar subwatt power levels. AMD estimates that Bobcat will deliver 90% of the performance of today's mobile-PC processors in half the die area. [August 30, 2010]

• Figure 1: AMD Bobcat block diagram.

• Figure 2: Bobcat pipeline diagram.

• Table 1: Key parameters for AMD's Bobcat, Bulldozer, and Athlon Neo.

• Table 2: Comparing AMD's Bobcat with Intel's Atom and Via Technologies' Nano.

(With Linley Gwennap)

AMD has its head in the clouds. Its new Opteron 4100 server processors are intended for cloud-computing data centers that buy servers by the truckload. With prices starting at $99 per chip and typical power as low as 32W, Opteron 4100 processors are challenging Intel's lowest-power Xeons in servers having one or two sockets. Although they can't match Xeon's most power-efficient models, they offer a less expensive alternative while still going easy on the electricity. These prices and power levels may seem low for server processors, but at AMD, $99 buys a quad-core chip running at 2.2GHz, and 32W represents 100% utilization for a server processor with six CPUs. In all, AMD has introduced nine new Opteron 4100 processors. [August 9, 2010]

• Figure 1: AMD Opteron 4100 and Opteron 6000 block diagrams.

• Table 1: Key parameters for AMD's new 4100-series server processors.

• Table 2: AMD's energy-efficient Opteron versus Intel's low-power Xeon.

• Table 3: Comparison of low-priced versions of Opteron and Xeon.

• Sidebar: Power Plays: ACP vs. TDP

NetLogic is unleashing its first barrage of networking and communications processors since acquiring RMI last year. Nine new chips are scheduled to sample this fall, each with the four-way multithreading and four-issue superscalar features of the previously announced eight-core XLP832. The new chips have one, two, four, or eight CPUs. The single-core XLP104, XLP204, and XLP304 processors are designed for small-business networking equipment supporting packet-throughput rates of 100Mbps to 4Gbps. For enterprise equipment requiring packet rates of 2Gbps to 40Gbps, NetLogic announced the dual-core XLP208, XLP308, and XLP408, plus the quad-core XLP316 and XLP416. At the high end of the family, the previously announced eight-core XLP832 will be joined by another eight-core chip, the XLP432. These two chips, which are designed for network infrastructure, scale from 10Gbps to 160Gbps. [July 26, 2010]

• Figure 1: Multithreading and superscalar execution in NetLogic's EC4400.

• Figure 2: NetLogic EC4400 CPU block diagram.

• Figure 3: NetLogic XLP832 block diagram.

• Figure 4: NetLogic's interchip interface (ICI).

• Table 1: Key parameters for NetLogic's XLP family.

• Table 2: Comparing NetLogic's XLP308 with processors from Cavium, Freescale, and Intel.

• Table 3: Comparing NetLogic's XLP208 with processors from Cavium and Freescale.

FPGA startup Tier Logic looks doomed after failing to raise enough money to move its first chips into production. The company, founded in Silicon Valley in March 2002, has spent about $20 million from its first-round investors and needs another $20 million to $30 million to bring its chips to market and reach breakeven. Tier Logic has operational samples of its first programmable-logic chips and has already taken orders from early customers. The company had planned to begin production by the end of this quarter. [July 19, 2010]

Freescale Semiconductor is making the leap to 2.2GHz and 64 bits. Although Intel and most MIPS-based competitors are already shipping 64-bit network processors, Freescale has stuck with the 32-bit Power Architecture CPUs that have been the cornerstone of its PowerQuicc line since the 1990s. Although Freescale will continue making 32-bit processors for years to come, its new P5-series chips in the QorIQ family will introduce a 64-bit Power Architecture core, which is capable of multigigahertz clock speeds. [July 5, 2010]

• Figure 1: Freescale QorIQ P5020 block diagram.

• Table 1: Freescale Semiconductor's QorIQ family.

• Table 2: Comparison of Freescale's new QorIQ P5 chips with existing Freescale chips.

• Table 3: Comparison of Freescale's QorIQ P5 series with competitors.

• Table 4: Comparison of Freescale's QorIQ P3041 with two quad-core competitors.

Kilopass, already an established player in nonvolatile memory (NVM), has introduced an improved version of its antifuse one-time-programmable (OTP) memory. Called Gusto, it's licensed as process-portable intellectual property (IP). It is the industry's first 4Mb OTP, quadrupling the capacity of existing OTP memories. It's large enough to store boot code and system firmware, rather than just code patches, configuration code, and trim settings for analog components. In addition, Kilopass claims Gusto reads memory two to four times faster, cuts active power consumption by an order of magnitude, and slashes current leakage in standby mode by a factor of 40. [June 14, 2010]

• Figure 1: Two-transistor antifuse bit cell.

• Figure 2: Antifuse bit-cell circuit diagrams.

• Figure 3: Electron micrograph of a Kilopass 2T antifuse bit cell at 40nm.

• Figure 4: XPM versus Gusto area comparison.

• Figure 5: Integration comparison of two hypothetical smartphones.

• Table 1: Gusto versus XPM.

• Table 2: Comparison of nonvolatile-memory (NVM) technologies.

Intel's troubled manycore-processor project is steering away from discrete 3D graphics in favor of high-performance computing (HPC), mainly for scientific and engineering applications. It's a wise maneuver that will salvage Intel's investment in the Larrabee project, and the new direction is better suited to Intel's experience and expertise. But it won't avoid a collision with Nvidia, which is surging into the same market. Intel revealed new details about its HPC strategy at the recent Super Computing Conference in Hamburg, Germany. The x86-based family of GPUs code-named Larrabee will spawn a new family of manycore processors code-named Knights. Both Larrabee and Knights can integrate dozens of x86 processor cores on a single chip. Intel now refers to this technology as the Many Integrated Core (MIC) architecture. [June 15, 2010]

(With Linley Gwennap)

Moorestown is Intel's code-name for a platform that includes a highly integrated Atom processor, a lower-power system-logic chip, a mixed-signal chip, low-level software, and improved system-level power management. The platform is intended for high-end smartphones, tablet computers, and the handheld computing devices that Intel formerly called mobile Internet devices, or MIDs. It will compete with processors designed for trendy products like the Apple iPhone, Nexus One, and Nokia N900, but probably not with more-integrated processors designed for mainstream smartphones, like the Blackberry Bold and Blackberry Curve. [May 31, 2010]

• Figure 1: Menlow versus Moorestown integration.

• Figure 2: Lincroft block diagram.

• Figure 3: Die-photo comparison of Lincroft versus Silverthorne.

• Figure 4: Briertown block diagram.

• Figure 5: Lincroft's burst mode.

• Figure 6: Thermal images of Lincroft in two different power states.

• Figure 7: Forecast of smartphone processor shipments from 2005 to 2014.

• Table 1: Power states for systems built with Intel's Moorestown chip set.

• Table 2: Estimated battery life of a Moorestown smartphone.

• Table 3: Comparison of Intel's Moorestown with leading smartphone processors from Texas Instruments and Qualcomm.

• Sidebar: Atomic Smartphones

• Sidebar: Moorestown Goes Embedded

• Sidebar: Decoding Intel's Code Names

Broadcast television in America, once described as a vast wasteland, now looks more like prime real estate. Or rather, the radio-frequency spectrum that broadcast TV occupies is the suddenly valuable property. So valuable that some people in the telecommunications industry want to seize all that RF spectrum for wireless telephony and banish terrestrial TV broadcasting to the dustbin of history. However, the real issue isn't the alleged obsolescence of broadcast TV. It's the shortage of high-quality RF spectrum for wireless data services—in particular, wireless services for smartphones and tablets. The wireless telcos and handset vendors are painting a marvelous vision of the future in which everyone carries a wireless device that delivers a dazzling array of features and services. Unfortunately, there isn't enough spectrum available to make the vision come true. [April 30, 2010]

Apple's stealthy acquisition of Intrinsity is the latest strategic move toward becoming a fully integrated consumer-electronics company. To differentiate its products and justify their higher prices, Apple must do more than wrap trend-setting industrial design and slick system software around other suppliers' standard parts. By developing custom SoCs and embedded-processor cores, Apple is assuming more risk, but the potential payoffs are great: less dependence on third-party suppliers, greater differentiation, higher retail prices, and richer profit margins. Now, Apple is absorbing Intrinsity, a small Austin-based company that sells embedded-processor cores, circuit-design tools, design services, and innovative intellectual property. Microprocessor Report has been covering Intrinsity for ten years—or even longer, counting the company's earlier incarnations as EVSX and Exponential Technologies. [April 26, 2010]

• Photo: The main applications processor in the iPad is an Apple-designed SoC, called the A4. It's based on a 1.0GHz ARM-compatible processor core—either a conventional ARM Cortex-A8 or Intrinsity's souped-up Hummingbird core, which is fully compatible with the Cortex-A8.

ARM is pitching its new Cortex-M4 processor as a digital signal controller (DSC)—the first time ARM has so described one of its processor cores. Essentially, a DSC crosses a digital signal processor (DSP) with a microcontroller (MCU) for double duty in controller applications that need a little signal processing. But, in fact, the Cortex-M4 is not a departure for ARM. It's more like a bridge between the ARM9, ARM11, and Cortex-M families. It adopts the same DSP and SIMD extensions introduced with the ARM9E processor core in 1999, later inherited by the ARM11 family in 2002. In essence, the Cortex-M4 provides a Cortex upgrade path for existing ARM9 and ARM11 designs. It can also upgrade designs based on fellow members of the Cortex-M family—the Cortex-M0 and Cortex-M3. [April 12, 2010]

• Figure 1: ARM Cortex-M4 block diagram.

• Figure 2: The ARMv7-M ISA as implemented in the Cortex-M family.

• Table 1: Single-cycle MAC instructions for the ARM Cortex-M4.

• Table 2: ARM Cortex-M4F floating-point instruction set.

• Table 3: Feature summary of the ARM Cortex-M4, Ceva TeakLite-II, Tensilica ConnX D2, Tensilica Diamond Standard 212GP, and Virage Logic ARC 610D.

Tabula, a Silicon Valley startup, has announced new programmable-logic devices that emulate three-dimensional stacked chips by rapidly reconfiguring their two-dimensional fabrics. With these devices, the third spatial dimension exists for only a split-second slice of time. Tabula's devices can completely reconfigure their fabrics up to 1.6 billion times per second. That's about one million times faster than conventional FPGAs. Rapid reconfiguration makes the physical fabric seem much larger than it really is. Tabula's first-generation chips can reuse the same physical gates for as many as eight different functions. In this way, a Tabula chip can match the capacity of an FPGA that's larger and more expensive. [March 29, 2010]

• Figure 1: Like a conventional FPGA/PLD, a Tabula 3PLD has only one physical fabric. By rapidly reconfiguring the fabric, each physical gate can perform up to eight different functions.

• Figure 2: Tabula uses time to emulate the third spatial dimension, making one fabric seem like eight fabrics stacked together. Each configuration is called a "fold" because it folds time into space.

• Figure 3: Tabula uses transparent latches as "time vias" to pass signals forward in time from one fold (fabric configuration) to another.

• Figure 4: In a Tabula chip, time isn't linear. It's an endless loop, because the last fold wraps around to the first fold. The virtual stack is really a torus.

• Figure 5: Tabula's first-generation devices run at 1.6GHz, but the perceived user clock speed depends on the number of folds. With eight folds—the maximum in these first devices—the "user clock rate" is 200MHz.

• Figure 6: As chip-fabrication technology improves, Tabula's 3PLDs may derive greater benefits from Moore's law. Faster clock speeds allow Tabula to add more folds to its virtual 3D fabric. This has implications for interconnects, as well as for gate density.

• Figure 7: Memory access in a Tabula Abax 3PLD. Although Tabula's chips use single-ported SRAM instead of dual-ported SRAM for user memory, different function blocks can independently access the same memory during each fold.

• Figure 8: Physical layout of logic tiles in a Tabula 3PLD.

• Figure 9: Floor plan of Tabula's Abax A1EC06, the highest-end 3PLD that Tabula has announced so far.

• Table 1: Feature comparison of Tabula's first four Abax 3PLDs.

• Sidebar: Another Three-Dimensional FPGA Debuts [Tier Logic]

It is with great sadness that we report the passing of our longtime colleague, Ellen Clements. Few readers of Microprocessor Report are familiar with Ellen, because her name didn't appear in the newsletter. Yet, for 17 years, Ellen was one of the people who worked behind the scenes to ensure its quality.

As far as anyone can remember, Ellen was the only copy editor in the 23-year history of Microprocessor Report. She began editing the newsletter in 1993, six years after it was founded by Michael Slater in 1987. As a freelance contractor, Ellen edited every article for grammar, spelling, and style. She also maintained our in-house style guide.

Ellen had a long career in Silicon Valley as an editor, ghost writer, editorial consultant, and industry analyst. She entered the field in 1977 as an analyst for Dataquest, covering minicomputers and printers. In addition to copy editing for Microprocessor Report, she worked with many other clients.

Her academic background was eclectic. Ellen graduated from the Bronx High School of Science in 1950, then earned a B.A. in English from Hunter College (City University of New York) in 1961. She did graduate work in sociology, anthropology, and linguistics at New York University, followed by additional study in German at the University of Vienna. Later, after moving to Silicon Valley, she attended De Anza College and Foothill Community College.

Ellen was an extrovert, an excellent conversationalist, a dreamer, and a romantic in the European sense. She loved opera and Shakespeare.

Ellen's passing was sudden and unexpected. She was working until her last day. In-Stat and the staff of Microprocessor Report offer our condolences to her family and especially to her surviving son and daughter, Duncan and Amanda. Ellen, we will miss you. [March 29, 2010]

It's not sunset yet. Now that Oracle's $7.4 billion acquisition of Sun Microsystems has closed, Oracle has made a public commitment to keep Sun's most important products and technologies shining. Those technologies include the SPARC microprocessor architecture and Java software platform. In late January, hundreds of customers, industry analysts, and reporters gathered at Oracle's headquarters in Redwood Shores, California, to hear Oracle and former Sun executives describe their plans for the merged company. To be sure, the presentations were glossy and often lacked detail. However, the following messages were clear: Sun will not be drastically downsized in a quest for quick profits; Oracle is reinvesting in Sun's key product lines, including SPARC, Solaris, and Java; and Sun's hardware completes Oracle's evolution into a vertically integrated enterprise-technology company, much like IBM in the 1960s. Oracle didn't acquire Sun solely for the software, as some observers speculated. [February 22, 2010]

• Photo: IBM's advertising for new POWER7-based servers unmistakably shows a sun in eclipse, but Oracle is fighting the FUD.

As embedded applications demand more performance, we're seeing more interest in licensable microprocessor cores specifically designed for symmetric multiprocessing (SMP). Of course, chip designers can use any processor cores for this purpose, but only a few cores have the built-in features, coherency control, and coherent debugging that make SMP easier to implement. ARM introduced the ARM11 MPCore in 2004, followed by the Cortex-A9 MPCore in 2008 and Cortex-A5 MPCore last year. MIPS Technologies introduced the MIPS32 1004K Coherent Processing System in 2008. All these cores are licensable 32-bit embedded processors supporting two-, three-, or four-way SMP with coherent memory systems. Now IBM is joining the race with the new PowerPC 476FP. Top speed exceeds 2.0GHz, or 1.6GHz under worst-case conditions. It has an FPU, and it supports coherent SMP systems with up to eight cores—twice as many cores as ARM or MIPS. [February 16, 2010]

• Figure 1: IBM PowerPC 476FP block diagram. This is one of the most complex 32-bit embedded-processor cores yet seen.

• Table 1: Feature comparison of the IBM PowerPC 476FP, ARM Cortex-A9 MPCore, MIPS 1004Kf, and ARM Cortex-A5 MPCore. All these 32-bit licensable embedded-processor cores are designed for coherent symmetric multiprocessing.

It's a race to the bottom—in a good way. The trend of replacing 8- and 16-bit microcontrollers with faster 32-bit devices has processor vendors rushing to shrink their cores to tinier dimensions. The smaller the core, the smaller the compromise in power consumption and cost when developers leave their 8- and 16-bit chips behind. The latest entry in this race is the ARC 601. It's the first new processor core Virage Logic has introduced since acquiring ARC International in September 2009. Although the ARC 601 is a relatively minor variation of the five-year-old ARC 605, it affirms that Virage Logic is committed to the ARC product line and isn't retreating before market leader ARM. [January 19, 2010]

• Figure 1: Two closely related microarchitectures form the basis of the ARC microprocessor product line.

• Table 1: ARC 601 metrics in three TSMC fabrication processes: 130nm-G, 90nm-G, and 65nm-GP.

• Table 2: Feature comparison of the Virage Logic ARC 601, ARM Cortex-M0, Cambridge Consultants XAP5a, Cortus APS3, MIPS Technologies MIPS32 M14K, and Tensilica Xtensa 8 processors.

Virtual reality is so...1990s. Sure, artificial environments are beguiling, whether they are created for videogames (World of Warcraft), virtual worlds (Second Life), Hollywood blockbusters (Avatar), or professional training (flight simulators). But now, virtual reality is looking like a stepping stone toward a grander concept: augmented reality. Augmented reality combines some features of virtual reality with actual reality. It can overlay a live view of the real world with computer-generated graphics or textual information, building an enhanced version of reality that's easier to interpret or navigate. Sometimes, augmented reality fabricates astonishing illusions that are entertaining as well as informative. Eventually, actual reality may come to seem drab, confusing, even dangerous. [December 28, 2009]

• Photo 1: Ludwig Fuchs of RTT AG and Nvidia CEO Jen-Hsun Huang demonstrate augmented reality at the GPU Technology Conference.

• Photo 2: Google Goggles can identify books and paintings photographed with an Android smartphone camera.

• Photo 3: Google Goggles can identify places of interest in live video images captured with an Android smartphone.

Since the 1990s, AMD and Intel have been marketing their microprocessors directly to consumers, using strategies that resemble the mass marketing of automobiles, fast food, laundry detergent, and other consumer products. But it wasn't always that way. In the 1980s, the idea seemed as silly as marketing capacitors to the general public. The transition of microprocessors from anonymous electronic components to consumer products is a fascinating study that was the subject of a recent discussion panel at the Computer History Museum in Silicon Valley. But it's not just a history lesson. The coming collision between ARM and Intel in smartphones could be the force that brings PC-style microprocessor marketing to this new frontier. [December 14, 2009]

• Photo 1: A discussion about microprocessor marketing at the Computer History Museum brought together five panelists: moderator David Laws, formerly of AMD; Jack Browne, formerly of Motorola; and Melissa Rey, Claude Leglise, and Dave House, formerly of Intel.

• Photo 2: Claude Leglise was Intel's marketing manager for all x86 processors from the 8086 to the 486.

• Photo 3: Melissa Rey was a marketing communications manager at Intel who promoted all the x86 processors from the 8086 to the 386.

• Photo 4: Dave House, a former Intel senior vice president, helped run Intel's microprocessor business from 1978 to 1991.

• Photo 5: Jack Browne was the marketing manager for Motorola's high-end microprocessors from 1981 to 1992.

Tensilica is introducing two new versions of its configurable embedded-processor cores: the Xtensa LX3 and Xtensa 8. In addition to having new features, they are generally smaller and faster than their predecessors and use less power when fabricated in the same CMOS process. The Xtensa 8 core is the smallest base configuration of Tensilica's Xtensa architecture and is intended primarily for 32-bit microcontrollers. The Xtensa LX3 is much more configurable than Xtensa 8 and is intended primarily for data-plane processing and signal processing. New features include ConnX 16-bit DSP extensions, a smaller version of Tensilica's Vectra LX DSP engine, a double-precision floating-point math accelerator, more system-bus options, better SystemC modeling, and code enhancements for C and C++ programmers. [November 30, 2009]

• Figure 1: Tensilica's DSP product line. All these DSP cores were based on the Xtensa LX2 and are moving to Xtensa LX3.

• Figure 2: New asynchronous bus bridge for the Xtensa LX3.

• Figure 3: Tensilica Xtensa LX3 block diagram.

• Table 1: Software emulation vs. hardware acceleration for double-precision floating-point operations, measured in clock cycles.

• Table 2: Performance comparison, Xtensa LX3 vs. Xtensa LX2.

• Table 3: Tensilica's Xtensa LX3 performance estimates, assuming two different fabrication processes, core configurations, and design flows.

• Table 4: Feature comparison of the Tensilica Xtensa LX3, ARM Cortex-A5, MIPS Technologies MIPS32 74K, MIPS32 24KE, and Virage Logic ARC 750D.

• Sidebar: Tensilica Debuts Xtensa 8 Core

Smaller is usually better for embedded processors, so MIPS Technologies is slimming down its 1980s-vintage instruction-set architecture. A new set of 16- and 32-bit instructions—dubbed microMIPS—uses less memory than existing 32-bit MIPS instructions and the 16-bit extensions added in the 1990s. MicroMIPS will debut early next year in two new embedded-processor cores, the MIPS32 M14K and MIPS32 M14Kc. The M14K is an improvement on the MIPS32 M4K processor, introduced in 2002. Its bigger brother, the M14Kc, is an improvement on the MIPS32 4KEc processor, introduced in 2003. [November 16, 2009]

• Figure 1: The new MIPS32 M14K and MIPS32 M14Kc processor cores introduce the microMIPS 16/32-bit instruction set and anchor the lower end of the MIPS product line.

• Figure 2: MIPS32 M14K processor block diagram.

• Figure 3: M14K processor flash-memory accelerator.

• Figure 4: Interrupt chaining in the MIPS32 M14K and M14Kc processors.

• Figure 5: MIPS32 M14Kc processor block diagram.

• Table 1: MicroMIPS instruction set.

• Table 2: MIPS32 M14K and M14Kc processor power/performance comparison.

• Table 3: Feature comparison of the MIPS32 M14K, M14Kc, M4K, 4KEc, ARM Cortex-A5, and Cortex-M3 cores.

Multicore processors are becoming so commonplace that even basic cellphones, MP3 players, and other mobile embedded systems are embracing them. That's why ARM has announced its smallest Cortex A-series multiprocessor core, the Cortex-A5. In a single-core configuration, it's small enough for workhorse microcontrollers, but a four-horse team of them can haul much bigger loads. Code-named Sparrow, the Cortex-A5 is the third member of the Cortex-A family. Although it's smaller and slower than the Cortex-A8 or Cortex-A9 MPCore, it supports coherent multiprocessing with up to four cores, as well as uniprocessor configurations. ARM is positioning the 32-bit Cortex-A5 as a superior substitute for the five-year-old ARM1176JZ(F)-S and a major upgrade from the eight-year-old ARM926EJ-S. [October 26, 2009]

• Figure 1: Even in a uniprocessor configuration, ARM's new Cortex-A5 is faster than similar members of the ARM9 and ARM11 families and is much more energy efficient.

• Figure 2: ARM Cortex-A5 block diagram.

• Figure 3: ARM Cortex-A5 pipelines.

• Figure 4: ARM Cortex-A5 trial layout.

• Figure 5: ARM Cortex-A5 quad-core block diagram.

• Table 1: Feature comparison of the Cortex-A5, Cortex-A8, ARM1176JZ(F)-S, ARM926EJ-S, and Cortex-M3.

• Table 2: Feature comparison of the ARM Cortex-A5, Cortex-A9 MPCore, ARM11 MPCore, and MIPS32 1004K processors.

Nvidia's next-generation GPU architecture, code-named Fermi, adds powerful new features for general-purpose computing. Fermi processors will continue to shoulder the graphics workloads in PCs, but they are taking the largest step yet toward becoming equal-partner coprocessors with CPUs. Fermi is the first GPU architecture to have ECC-protected memory and to be fully programmable in C++. Double-precision floating-point performance is eight times faster than Nvidia's previous generation. With numerous additional improvements, Fermi significantly advances the state of the art in this field. [October 5, 2009]

• Figure 1: Nvidia estimates that the total available market for GPU computing is at least half as large as the desktop-PC market for GPUs.

• Figure 2: CUDA-core block diagram.

• Figure 3: Streaming-multiprocessor block diagram.

• Figure 4: CUDA multithreading in the Fermi architecture.

• Figure 5: Fermi architecture block diagram.

• Figure 6: Fermi's memory hierarchy.

• Figure 7: Memory allocation with CUDA.

• Figure 8: CUDA kernels are modified versions of conventional functions written in C.

• Table 1: Comparison of Nvidia's three CUDA-capable GPU architectures: G80, GT200, and Fermi.

Another future has arrived. Last year, my colleague Max Baron analyzed competing technologies for picoprojectors—tiny video projectors occupying less than a cubic inch of space. (See MPR 12/8/08, "The New Peripheral is Almost Here".) Although picoprojector modules began appearing in small presentation projectors and other specialized devices, the technology hadn't quite hit the consumer mainstream. Then, in August, Nikon revealed the world's first digital camera with a built-in projector. The Coolpix S1000pj displays still photos and video clips at VGA resolution. Eventually, picoprojectors will replace bulky video projectors and will liberate portable video from the confining dimensions of tiny LCDs. More important, picoprojectors will allow inventors to create new products we haven't dreamed of yet. [September 28, 2009]

• Photo: Nikon Coolpix S1000pj.

Three recent business deals are of special interest to programmers and chip developers. First, Intel has acquired Cilk Arts and RapidMind, two small but brainy companies specializing in development tools for parallel programming. Second, Virage Logic is buying ARC International, which will alter the competitive landscape for licensable embedded-processor cores. All these moves are further evidence that forward-thinking companies are taking advantage of recessionary prices to strengthen their positions for recovery. Intel's late-summer purchases of Cilk Arts and RapidMind (for prices undisclosed) follow its early-summer $884 million acquisition of Wind River Systems. Virage Logic's bid for ARC will add synthesizable microprocessor cores and configurable-processor technology to its growing portfolio of licensable intellectual property (IP). [September 14, 2009]

As personal computing migrates from desktops to pockets, Intel knows it must push the x86 architecture into ever-smaller, lower-power, lower-cost systems. But investors and financial analysts are watching the lower prices of Intel processors and worry that Atom will cannibalize Intel's most lucrative line of business. Their worries aren't entirely unfounded. Never has the price difference between Intel's low-end and high-end PC processors been so wide and the performance difference so narrow. But the new markets offer tremendous opportunities for growth, so Intel must pursue them, even at the risk of price erosion. [August 24, 2009]

Tensilica's ConnX Baseband Engine—a CPU/DSP core optimized for wireless baseband processing—signals a new direction for the 12-year-old company. Although Tensilica says most of the 350 million processor cores it has shipped are performing DSP tasks already, Tensilica has always styled itself as a vendor of configurable RISC CPUs. Now, with ConnX BBE, the company is making a major play for DSPs. ConnX BBE has provisions for multicore designs and is suitable for infrastructure equipment as well as for next-generation cellphones. [August 10, 2009]

• Figure 1: In-Stat's forecast of 4G/LTE cellular handset sales.

• Figure 2: ConnX Baseband Engine block diagram.

• Figure 3: Tensilica's compiler converts ANSI C into vectorized machine code.

• Figure 4: System I/O with a single-core ConnX BBE design.

• Figure 5: Hardware message passing in a dual-core ConnX BBE design.

• Figure 6: Distributed shared memory in a quad-core ConnX BBE design.

• Figure 7: Input chain of an LTE radio baseband.

• Table 1: ConnX BBE performance for various FFT and FIR functions.

• Table 2: Feature comparison of the Tensilica ConnX Baseband Engine, Ceva-XC DSP, and NXP CoolFlux BSP.

ARM's fastest microprocessor core keeps getting faster. Only five months ago, Texas Instruments announced a 1.0GHz ARM Cortex-A8 in future OMAP3 cellphone chips. Now Intrinsity is unveiling a 1.0GHz Cortex-A8 accelerated with dynamic logic. Intrinsity's new core, code-named Hummingbird, is functionally identical to a Cortex-A8 implemented in standard-cell static logic. Intrinsity says Hummingbird can reach 1.0GHz under worst-case conditions at 1.2V when fabricated in a 45nm-LP low-leakage process. It could exceed that clock frequency in a faster but leakier 45nm-GP process. [July 27, 2009]

• Figure 1: Intrinsity Fast14 design flow.

• Table 1: Estimated Cortex-A8 performance in different implementations and fabrication processes.

For the first time, the world's most populous nation has licensed the MIPS microprocessor architecture directly from MIPS Technologies. The landmark deal ends all questions about the legitimacy of China's Godson and Loongson processors—MIPS-compatible chips developed independently by Chinese engineers. The official licensee is the Institute of Computing Technology (ICT) at the Chinese Academy of Sciences in Beijing. Although ICT is a government-owned academic and research institution, the MIPS licenses are full-fledged commercial contracts, not the limited academic licenses usually granted to universities. [July 13, 2009]

Recessions and depressions are national or global in scope, like epidemics and pandemics. But among individuals, the experience varies. Most people don't lose their jobs in an economic downturn or get sick when a disease breaks out. In tough times, wealth and health accrue even more value. For people who didn't lose their money in the 1930s, the Great Depression was the Great Opportunity. The same is true of today's Great Recession. Here's an analysis of recent changes in the semiconductor industry that were accelerated, if not wholly caused, by the recession. [June 29, 2009]

• Figure 1: Wind River's first-quarter revenue bookings, by market category.

• Photo: The SiCortex SC5832 had 5,832 processors and 8TB of memory, delivering 8.2 teraflops.

EEMBC's new CoreMark is a quick-and-dirty benchmarking program intended primarily for embedded processors. It isn't a substitute for the EEMBC suites, which remain a more sophisticated and comprehensive way of measuring performance. But CoreMark is free, portable, easy to use, and yields a single score that's easy to grasp. Can it finally retire the ancient Dhrystone benchmark? After some quick-and-dirty testing, Microprocessor Report found CoreMark to be a major improvement. [June 8, 2009]

• Figure 1: CoreMark instruction profile (Power Architecture).

• Figure 2: CoreMark instruction profile (x86).

• Figure 3: Typical CoreMark results.

• Table 1: CoreMark and Dhrystone scores for three Intel x86 processors, as benchmarked by MPR.

Why would Apple design custom chips? A recent Wall Street Journal article alarmed critics, but Apple has good reasons for hiring more chip designers. Apple is a consumer-electronics company, not just a computer company, and custom SoCs are crucial to Apple's strategy. [May 26, 2009]

• Photo: On June 29, 2007, early adopters besieged Apple Stores to buy the first iPhone. To create this kind of frenzy, Apple must differentiate its products from those of competitors.

• Figure 1: Apple revenues, Q1 2009. All those little iPods add up. At $3.37 billion for the quarter, they account for the biggest share (33.2%) of Apple's revenues. Even the iPhone generates more revenue ($1.24 billion) than Mac desktops.

• Figure 2: Apple's iPod unit sales, 2002-2009. Today, the iPod so dominates the audio market that it's easy to forget Apple wasn't the first to ship an MP3 player. Despite a late and relatively slow start, the iPod soared to popularity. This chart also reveals the seasonal pattern of iPod sales—a Christmas holiday cycle that's typical of consumer electronics.

Not everyone thinks Moore's law is a quota. Some CPU architects strive to design smaller and smaller microprocessor cores, bucking the trend toward larger processors. In the Lilliputian world of microcontrollers and deeply embedded systems, smaller is definitely better. This report compares the ARM Cortex-M0, Cambridge Consultants XAP5a, Cortus APS3, and Tensilica Diamond Standard 106Micro. [May 11, 2009]

• Figure 1: Cortus APS3 block diagram.

• Figure 2: Cortus APS3 coprocessor interface.

• Figure 3: Peripheral-IP blocks for the Cortus APS3 processor core.

• Figure 4: Cambridge Consultants XAP5a block diagram.

• Figure 5: Tensilica Diamond Standard 106Micro block diagram.

• Table 1: Feature comparison of the ARM Cortex-M0, Cambridge Consultants XAP5a, Cortus APS3, and Tensilica Diamond Standard 106Micro.

• Sidebar: Gate Count? Depends Who's Counting
  • Sidebar Table: Estimated gate counts when implementing the Cortus APS3 processor core in different fabrication processes.

It'll be a long time—maybe forever—before someone invents a magic compiler that transforms existing serial code into optimized parallel code. Meanwhile, hard-pressed programmers are tackling the job by hand. Now their task will be a little easier. CriticalBlue has introduced Prism, a code-analysis tool that helps developers extract thread-level and system-level parallelism from legacy programs written in sequential code. After running the target program in a software simulator that captures dynamic trace data, developers can use Prism to analyze the results in numerous ways. Most important, Prism helps developers explore various what-if scenarios so they can make intelligent decisions before rewriting any code. [April 27, 2009]

• Figure 1: Prism assumes most programmers will implement multithreading with the Posix Thread API.

• Figure 2: Prism analyzes dynamic trace information to identify three classic types of data dependencies.

• Figure 3: Finding data dependencies with Prism.

• Figure 4: Analyzing source code with Prism.

• Figure 5: A multithreaded data-flow graph in Prism.

• Figure 6: After the programmer forced some data-dependent operations to execute serially, Prism's data-flow graph shows all data flowing forward in time.

• Figure 7: Software developers can quickly add or subtract processor cores to test a program with different multicore configurations.

• Figure 8: This composite of two cropped screen photos shows the results of forcing a function to run in parallel threads on a quad-core processor.

• Figure 9: Prism's hot-spot finder.

• Figure 10: Prism's hot-spot finder (detail).

• Figure 11: Prism's function-call graph.

• Figure 12: Prism's function-call graph (detail).

Free link to this article: Going Parallel With Prism

Memory prices have fallen so dramatically that flash-memory cards are now cheaper than film, even if you use them only once. And that comparison doesn't even add the cost of processing the film. But therein lies a paradox. Eventually, this trend will drive memory cards into obsolescence before film. Bear with me—my analysis may influence your future system designs. [March 30, 2009]

• Photo: Can you spot the soon-to-be-obsolete image-recording medium in this picture? Don't be too quick with your answer.

Intel and TSMC have announced a new collaboration in which Intel will design customer-specific SoCs based on the Atom microprocessor core. TSMC will offer peripheral blocks for the SoC designs and manufacture the chips in its fabs. For Intel, it's the first step toward x86 licensing since the 1980s, when the company sold second-source licenses to AMD and other suppliers. Make no mistake: this deal is aimed squarely at ARM. Intel wants to push the x86 architecture into smartphones and other low-power embedded systems, which ARM dominates. Although Intel isn't close to adopting a licensing model as open as ARM's, this is still a big step for a company that guards the x86 like a family heirloom. [March 30, 2009]

• Table 1: The new Intel/TSMC custom-SoC program for Atom differs markedly from processor-IP licensing models, as exemplified by ARM.

The name says it all: Cortex-M0. As in "M-Zero." Unless ARM starts naming its processors with negative numbers, the new Cortex-M0 will always be the smallest member of the growing Cortex-M family. Announced February 23, it's a 32-bit synthesizable processor core for microcontrollers and deeply embedded applications. The Cortex-M0's minimum usable configuration is a mere 12,000 gates. To put that in perspective: it's about one-third the size of the ARM7TDMI hard macro—itself a small processor core, designed in the mid-1990s when everything was smaller. Even the base configurations of customizable processor cores from ARC International, MIPS Technologies, and Tensilica aren't this tiny. Anything tinier is probably an 8- or 16-bit processor. [March 2, 2009]

• Figure 1: ARM Cortex-M0 instruction set.

• Figure 2: ARM Cortex-M0 block diagram.

• Figure 3: Low-power state retention in the Cortex-M0.

• Figure 4: Cortex-M0 power profile.

• Table 1: Four 32-bit ARM processor cores suitable for microcontrollers and deeply embedded applications: the Cortex-M0, Cortex-M1, Cortex-M3, and ARM7TDMI-S.

• Table 2: ARM Cortex-M0 configuration options.

• Table 3: Feature comparison of the ARM Cortex-M0, ARC 605, MIPS32 M4K, and Tensilica 106Micro processor cores.

What do Intel microprocessors and Microsoft operating systems have in common with Fred Astaire and Ginger Rogers? All became more famous than the products of which they are parts, says a Harvard Business School professor. And, he says, Intel won fame by deciding in 1986 to stop licensing x86 designs to second-source manufacturers like AMD—a move that probably saved Intel from bankruptcy and radically changed the computer industry. These lessons and others are part of a case study that Professor Richard S. Tedlow teaches at Harvard Business School. However, Microprocessor Report has a few quibbles with his analysis, mainly because it doesn't go far enough. And it isn't a matter of mere historical interest. We think the changes wrought by the 386 are more relevant now than ever. As AMD struggles for survival, and after all known startups working on x86-compatible processors have crashed, Intel is nearer to capturing a worldwide monopoly of PC processors today than it was 23 years ago. [February 17, 2009]

• Photo 1: Professor Tedlow presented his Intel 386 case study as a lecture at the Computer History Museum on January 26.

• Photo 2: IBM's advertising campaign for the original IBM PC featured a Charlie Chaplin lookalike in "Little Tramp" costume.

• Photo 3: IBM's decision to adopt the x86 for the IBM PC was a watershed for the computer industry, but it took a while for Intel to realize it.

• Photo 4: In the 1980s, eight-bit CPU architectures like the 6502 were big sellers, especially in home computers from Apple, Atari, and Commodore.

• Table 1: AMD's evolving role as an alterative source for x86 processors since 1981.

• Sidebar: Designing the Intel 386

• Sidebar: How Intel's Manufacturing Got Big (by John Novitsky and Dave House)
  
  • Sidebar photo: Dave House was general manager of Intel's Microcomputer Group in 1985. At right is John Novitsky, who worked on the 32-bit ISA for the 386 processor.

• Related viewpoint article: Can Detroit Emulate Intel? (by John Novitsky)

As personal computers proliferate, malicious hackers have more targets. But we're so bombarded with warnings about anonymous attacks coming from the Internet that it's easy to overlook the potential threats closer to home. Consider the physical security of a personal computer—whether it's a desktop PC, laptop PC, mobile phone, or other device. Can everyone who handles it be trusted? My recent experience with a repair shop shows that we cannot. [January 26, 2009]

• Figure: This download log reveals that my computer was misused by a repair technician.

At Microprocessor Report, we are primarily technology analysts, not market analysts, so we don't make economic forecasts. Our fellow In-Stat analysts are not so lucky. Since the economy sharply worsened in September, they have struggled to update their market forecasts for 2009 and beyond—a daunting task. Even the world's top economists have been rocked by the Wall Street meltdowns, government bailouts, and financial upheavals of recent months. It's difficult to anticipate what will happen a few weeks from now, much less months or years in the future.

Unfortunately, many people believe our now collapsed bubble economy was a normal economy. As a result, they define recovery as the restoration of bubble-level business activity. This misconception is understandable for younger folks who have known nothing but bubbles. However, even some older people have forgotten what a normal-growth economy looks like. It's time for an attitude adjustment. [December 31, 2008]

In December, AMD started bundling the runtime package for its ATI Stream parallel-processing platform with the latest display driver for ATI graphics processors. As users download this driver, the installed base of Stream-capable systems could swell to more than two million PCs. Before, users had to download and install the free ATI Stream runtime separately. Over the past two years, Microprocessor Report has published in-depth articles on Nvidia's CUDA, the RapidMind Multicore Development Platform, and the PeakStream Platform. All are software-development platforms for parallel processing. (PeakStream's products went off the market after Google acquired the company in 2007.) This article analyzes ATI Stream. [December 22, 2008]

• Figure 1: AMD's nomenclature for an ATI GPU varies according to the target application.

• Figure 2: Each SIMD engine in an ATI GPU/stream processor contains multiple thread processors, and each thread processor contains multiple stream cores.

• Figure 3: ATI Stream programming model.

• Figure 4: Source code written in ATI Stream's flavor of C splits into two forks: code destined for the x86 CPU and code destined for the ATI GPU.

• Figure 5: The GPU ShaderAnalyzer utility for ATI Stream.

• Figure 6: This example code defines a kernel function in Brook+ C.

• Figure 7: An example main() function in Brook+ C.

• Sidebar: OpenCL Tries to Standardize Parallel Programming

Freescale Semiconductor is exploring a new line of business that has interesting implications for other chipmakers. Starting now, Freescale is offering design services to customers that want a custom SoC. Freescale will offer intellectual property (IP) for the chip, will design the chip, and will manufacture the chip. The customer provides a design specification and money. At first glance, it looks as if Freescale is merely launching a design-services business, just one more design house among many. But there's a catch. Unlike most design houses, Freescale has little interest in making SoCs entirely new from the ground up. Instead, the SoC must be based on an existing Freescale standard part or use a substantial amount of Freescale's existing IP. To customize the SoC for the target application, Freescale is willing to add or remove blocks and integrate some customer-provided IP or third-party IP. [November 17, 2008]

• Figure 1: Block diagram of Freescale's PowerQUICC II Pro MPC8360E.

The hottest presentation at the recent Hot Chips Symposium at Stanford University was the world's first look at the Godson-3, the latest generation of China's most powerful microprocessor family. It was the first time a Chinese CPU architect visited the U.S. to lift the bamboo curtain on a home-grown Chinese processor at a major technical conference. Among the revelations was a startling feature: more than 200 new instructions and other modifications that accelerate x86-to-MIPS dynamic binary translation. In other words, the Godson-3 applies hardware optimization to x86 emulation, much as Transmeta did with its Crusoe and Efficeon microprocessors. (The Godson-3 is also known as the Loongson-3 or Dragon-3.) [November 3, 2008]

• Figure 1: Block diagram of the Godson-3's GS464 processor core.

• Figure 2: Cluster of four GS464 processor cores sharing four coherent L2 caches.

• Figure 3: Two GS464 clusters linked together, forming an eight-core microprocessor.

• Figure 4: A massively parallel implementation of the Godson-3 could populate the on-chip mesh network with 16 or more quad-core clusters.

• Figure 5: GStera coprocessor block diagram.

• Figure 6: Quad-core Godson-3 die layout.

• Figure 7: Two examples of x86 virtual machines running atop a MIPS version of Linux on the Godson-3.

• Photo: The Godson-3 was presented at the Hot Chips Symposium by Zhiwei Xu, a professor at the Institute of Computing Technology, Chinese Academy of Sciences.

The old dream of a paperless office remains alluring, but the U.S. finally appears to be awakening from its nightmare of paperless voting. Gradually, election reformers are convincing public officials that paperless electronic voting machines are too flawed to win public confidence in the most important exercise of a democracy. Although much work remains to be done, we're seeing positive change since first editorializing on this subject in 2006. (See "Undo Electronic Voting".)

Politics is beyond the purview of Microprocessor Report, but we are alert to flagrant abuses of computer technology. A bread toaster that connects to the Internet and requires periodic firmware updates may offend our engineering sensibilities, but it's also funny, in a perverse way. A black-box voting machine that determines elections by running secret source code on untested hardware behind a poor user interface—and without a paper trail—is simply perverse. [October 27, 2008]

(Edited by Tom R. Halfhill)

This year marked the 20th anniversary of the Hot Chips Symposium at Stanford University in Palo Alto, California, sponsored by the IEEE Technical Committee on Microprocessors and Microcomputers. To celebrate, the organizers invited six industry experts to join a discussion panel: "Ready, Fire, Aim—20 Years of Hits and Misses at Hot Chips." They reviewed new microprocessors and architectures presented at the symposium since 1989 and attempted to sort out the successes and failures. Microprocessor Report has lightly edited the transcript of their discussion for clarity and has added comments and article references to help put some remarks into context. [October 20, 2008]

• Photo 1: The discussion panel included Howard Sachs, Telairity; David Ditzel, Intel; Michael Slater, Webvanta; Nathan Brookwood, Insight64; John R. Mashey, Techvisor; and David Patterson, University of California at Berkeley.

• Photo 2: Moderator Nick Tredennick.

• Photo 3: Microprocessor Report founder Michael Slater.

Intel is spreading the x86 everywhere. No longer satisfied with existing strongholds in PCs and servers, this year Intel has revived the x86 as a standalone embedded processor and has introduced the first highly integrated x86-based SoCs. And as early as next year, Intel will debut the first x86-based 3D-graphics processors. So far, graphics is the oddest addition to the x86's growing list of target applications. A 30-year-old CISC architecture designed for general-purpose processing would seem to be seriously handicapped against special-purpose GPUs, which are highly optimized for tasks like pixel shading and texture mapping. But Intel is undeterred. At Siggraph 2008—a graphics show, not a microprocessor conference—Intel unveiled the first technical details about its future x86-based GPU, code-named Larrabee. [September 29, 2008]

• Figure 1: Larrabee has a fully programmable graphics pipeline, augmented with only a little specialized logic.

• Figure 2: Block diagram of Larrabee's scalar and vector instruction paths.

• Figure 3: Block diagram of Larrabee's vector processing unit (VPU).

• Figure 4: Graphics performance of three action games on simulated Larrabee processors with eight to 48 cores.

• Figure 5: Preliminary benchmark testing on simulated Larrabee processors with eight to 64 cores.

• Figure 6: Larrabee's software stack.

• Figure 7: Larrabee's multithreading model.

• Figure 8: Block diagram of Larrabee's on-chip network.

The embedded-processor market resembles a wild costume party, with variety galore—from Little Bo Peep (8-bit MCUs) to the Incredible Hulk (massively parallel DSPs). Into this colorful riot wanders Intel, casually dressed by The Gap for a come-as-you-are party. Intel's first x86-based SoCs, announced July 23, are attired less appropriately than Intel would like. For now, they combine a PC processor core, a PC north-bridge chip, a PC south-bridge chip, and (optionally) a cryptography-acceleration chip. Consequently, they are relatively large and power hungry when compared with competing SoCs. But they are also fast, highly integrated, and definitely better than a system cobbled together with three or four separate Intel chips. [August 18, 2008]

• Figure 1: Intel EP80579 block diagram.

• Figure 2: Low-level cryptography acceleration on the Intel EP80579 with QuickAssist.

• Figure 3: IPsec acceleration on the Intel EP80579 with QuickAssist.

• Table 1: Summary of distinguishing features among the eight parts in the Intel EP80579 family.

• Table 2: Comparison of similar networking and communications processors from Broadcom, Cavium, Freescale, and Intel.

Imagine a world without measurements or statistical comparisons. Baseball fans wouldn't fail to notice that a .300 hitter is better than a .100 hitter. But would they welcome a trade that sends the .300 hitter to Cleveland for three .100 hitters? System designers and software developers face similar quandaries when making trade-offs with multicore processors. Even if a dual-core processor appears to be better than a single-core processor, how much better is it? Twice as good? Would a quad-core processor be four times better? The Embedded Microprocessor Benchmark Consortium (EEMBC) wants to help answer those questions. EEMBC's MultiBench 1.0 is a new benchmark suite for measuring the throughput of multiprocessor systems, including those built with multicore processors. [July 28, 2008]

• Figure 1: MultiBench 1.0 introduces the concept of work items and workloads instead of kernels.

• Figure 2: Screen shot of EEMBC's Workload Creator.

• Figure 3: Preliminary MultiBench results on an anonymous quad-core processor.

• Figure 4: Preliminary MultiBench results comparing two anonymous dual-core processors.

• Table 1: EEMBC MultiBench 1.0 workloads and the existing EEMBC benchmark suites (if any) from which they were adapted.

• Table 2: MultiBench composite scores and multicore scale factors for two different dual-core processors.

We keep hearing more complaints that it's hard to write software for multicore processors because there aren't enough development tools. Not enough tools? That's like complaining it's hard to buy Chinese products because there aren't enough Wal-Marts. The real problem with multicore processors is too many development tools—and the tools are often difficult to learn and use. [July 28, 2008]

They will be powerful and quick, but they won't be PowerQUICC. Instead of using the brand name that has been a household word since 1995—in the households of network engineers, that is—Freescale Semiconductor has unveiled a new name for its future communications processors. The new brand is QorIQ (pronounced "Core IQ"). Although the name doesn't seem like an upgrade, the chips look good. Among the first six QorIQ devices announced is the P4080, the first eight-processor multicore chip from Freescale. Some future QorIQ chips will have at least 16 cores. The PowerQUICC brand and product line aren't going away soon, but the vast majority of Freescale's new networking and communications processors will be QorIQ devices. [July 7, 2008]

• Figure 1: QorIQ P4080 block diagram.

• Figure 2: QorIQ P1-family block diagram.

• Figure 3: QorIQ P2-family block diagram.

• Table 1: Feature comparison of the six Freescale QorIQ chips announced to date: the P1010, P1011, P1020, P2010, P2020, and P4080.

• Sidebar: The New, Improved Power e500mc Processor Core
  • Figure: The Power Architecture embedded hypervisor.

For several years now, Microprocessor Report has covered the trend toward implementing and deploying SoC designs in the programmable logic of FPGAs instead of in the fixed logic of ASICs. In the past, programmable-logic devices were commonly viewed as prototype platforms, not as final products. FPGA developers received a big boost recently when Synplicity unveiled its ReadyIP initiative. ReadyIP allows soft-IP vendors to package their cores in a standardized format, so FPGA developers can easily integrate the IP using system-level design tools. Optionally, soft-IP vendors can protect their ReadyIP cores with encryption that still lets developers evaluate a design before purchasing a full license. And ReadyIP isn't specific to any particular brand of FPGAs. [June 16, 2008]

• Figure 1: ReadyIP design flow.

• Table 1: Feature comparison of 32-bit synthesizable processors approved by their vendors for deployment in FPGAs: the Altera Nios II/f v8.0, ARM Cortex-M1, Freescale ColdFire-V1, Gaisler Research LEON3, Tensilica Diamond Standard 106Micro, and Xilinx MicroBlaze v7.

• Sidebar: Freescale Offers ColdFire-V1 for FPGAs

Silicon Valley is buzzing over the final fates of two fabless-semiconductor companies: Montalvo Systems and P.A. Semi. One went bust, and the other was mysteriously acquired by Apple. The only industry gossip that wagged more tongues this spring was Yahoo's frigid response to Microsoft's takeover bid. [May 27, 2008]

ARM is enhancing its Cortex-M3 processor core with faster clock speeds, configurable debug logic, new power-saving features, and compatibility with third-party fault-tolerance technology. All the enhancements make the Cortex-M3 even more suitable for microcontrollers, but fault tolerance is especially important for automotive, medical, and military applications. Cortex-M3 Release 2.0 is compatible with a third-party fault supervisor from Yogitech, a company based in Pisa, Italy (home of the world's most fault-tolerant tower). [May 12, 2008]

• Figure 1: ARM's enhanced Cortex-M3 processor has an optional observation port called the faultRobust Diagnostic Interface that couples to Yogitech's fRCPU fault-supervisor module.

• Figure 2: Diagnostics recommended for ICs rated HFT=0 by the IEC61508 norm.

• Figure 3: A common way to design HFT=0 systems is to use redundant processor cores running in lockstep. A smaller diagnostic module, tightly coupled to the CPU, can provide enough diversity and safety while saving silicon and power.

• Figure 4: Yogitech faultRobust-CPU (fRCPU) block diagram.

• Figure 5: When Yogitech's fRCPU supervisor detects a CPU fault, it generates an error message.

• Figure 6: For higher degrees of fault tolerance (HFT>0), two processor cores and two of Yogitech's fRCPU supervisors can form a dual-channel system.

• Figure 7: Cortex-M3 Release 2.0 block diagram.

• Table 1: The IEC has defined these standards for fault tolerance in embedded subsystems. The higher the Safety Integrity Level (SIL), the higher the subsystem's availability.

Four-bangers are the low-end motors of the automobile world, but quad-core microprocessors are currently the hot rods of computing. On April 1, MIPS Technologies made it easier for chip designers to create quad-core SoCs by introducing the industry's first licensable processor core supporting four-way symmetric multiprocessing (SMP) and chip multithreading. A full implementation of the new MIPS 1004K Coherent Processing System with four dual-threaded cores offers the virtual equivalent of eight-way SMP. [April 28, 2008]

• Figure 1: Block diagram showing four-way SMP with the MIPS 1004K Coherent Processing System.

• Figure 2: Coherence-manager block diagram.

• Figure 3: Optional I/O coherence unit (IOCU).

• Figure 4: JPEG decompression on four different configurations of the MIPS 1004K CPS.

• Table 1: Comparison of dual- and quad-core MIPS 1004Kc CPS configurations with the single-core MIPS 34Kc processor.

• Table 2: Feature comparison of the MIPS 1004K CPS, ARM11 MPCore, and ARM Cortex-A9 MPCore.

In-depth 10,000-word report on Intel's new Atom family of low-power x86 microprocessors, formerly known as Silverthorne and Diamondville. Although Atom still uses too much power for most traditional embedded systems, by x86 standards it's a power-performance landmark. At launch, Atom's clock frequency will range from 800MHz to 1.86GHz, yet thermal design power (TDP) is a mere 0.65W-2.4W over that range. TDP is a worst-case metric, so typical workloads will draw much less wattage. Intel estimates the "average" power at 160-220mW and idle power at 80-100mW. Even the new Isaiah microarchitecture from VIA Technologies—formerly the low-power x86 leader—can't match Atom's TDPs. Atom completely redefines the low-power x86 landscape. [April 7, 2008]

• Figure 1: Atom pipeline diagram.

• Figure 2: Atom block diagram.

• Figure 3: Intel's page-rendering benchmarks for seven popular websites.

• Figure 4: Shmoo plot of Atom's voltage-frequency curve in two low-power states.

• Figure 5: Atom's power states.

• Figure 6: Atom die plot.

• Table 1: Intel's Atom lineup at launch.

• Sidebar: Atom's System Controller Slashes Power, Too
  • Figure: Poulsbo block diagram.

• Sidebar: Decoding the Code Names

Multicore processors are causing much consternation in the software-development community. Traditional single-threaded programs essentially gain nothing by running on microprocessors with multiple cores. Indeed, the program might even run worse. Multicore processors are in vogue because the power-dissipation penalties of higher clock speeds force CPU architects to find alternatives. The newly popular alternative is to integrate multiple processor cores in a single chip, clock the cores at a lower frequency, and tell programmers to rewrite their software. The solution that seems to be emerging is explicitly coded data-level parallelism. [March 31, 2008]

In-depth 6,000-word report: VIA's new Isaiah microarchitecture is a clean-slate x86-compatible design with superscalar pipelining, out-of-order instruction processing, speculative execution, multilevel dynamic branch prediction, larger on-chip caches, and one of the fastest FPUs in the industry. In addition, Isaiah is VIA's first 64-bit x86 processor. VIA previewed Isaiah (then known as Centaur CN) in 2004, but it's only now sampling in silicon and is scheduled to debut later this year. [March 10, 2008]

• Figure 1: Isaiah die plot.

• Figure 2: Isaiah block diagram.

• Figure 3: Isaiah's primary branch predictor.

• Figure 4: VIA's PowerSaver technology with TwinTurbo PLLs.

• Table 1: Isaiah's floating-point and media-processing performance.

In tech lingo, "IP" is an overloaded acronym that can mean "intellectual property" or "Internet Protocol." Now there may be a third definition: "impulse purchase." Intellectual-property vendor IPextreme has opened a retail website called the Core Store that makes buying IP for system-on-chip (SoC) development almost as easy as buying digital music. The Core Store sells synthesizable processor- and peripheral-IP cores at fixed, published prices. With a few mouse clicks, chip developers can review online documentation, buy the IP (Visa, MasterCard, and PayPal accepted), download the files, and begin working immediately. [February 11, 2008]

• Figure 1: Soft IP for sale on the Core Store's home page.

• Figure 2: Block diagram of a generic SoC that could be designed using National Semiconductor's fixed-price IP available at IPextreme's Core Store.

Nvidia's Compute Unified Device Architecture (CUDA) is a software platform for massively parallel high-performance computing on the company's powerful GPUs. Formally introduced in 2006, after a year-long gestation in beta, CUDA is steadily winning customers in scientific and engineering fields. At the same time, Nvidia is redesigning and repositioning its GPUs as versatile devices suitable for much more than electronic games and 3D graphics. For Nvidia, high-performance computing is both an opportunity to sell more chips and insurance against an uncertain future for discrete GPUs. [January 28, 2008]

• Figure 1: Nvidia's CUDA platform for parallel processing on Nvidia GPUs.

• Figure 2: Nvidia GeForce 8 graphics-processor architecture.

• Figure 3: Three different models for high-performance computing.

• Figure 4: CUDA programming example in C.

• Figure 5: CUDA's compilation process.

Free link to this article on Nvidia's website: Parallel Processing With CUDA

With the multicore era undeniably upon us, more talk is turning to the future implications of multicore processors. Of course, software development remains a big challenge, even provoking a recent article in The New York Times, of all places. But the discussion is equally spirited on the hardware side. One debate is about symmetric versus asymmetric multiprocessing. Should all the cores on a multicore chip be identical, or should some be specialized for different tasks? Another debate questions the value of core-level multithreading. How many threads make sense? In many ways, these debates echo the classic RISC versus CISC arguments of the 1990s—simplicity versus complexity, efficiency versus expediency. [December 31, 2007]

Once given up for dead, Transmeta is getting a second chance. Thanks to a $250 million settlement from Intel in a patent-infringement lawsuit, Transmeta is looking forward to a new future as an intellectual-property (IP) provider. But the company says it has no plans to resume making microprocessors. This article analyzes Transmeta's current situation, discusses Transmeta's future plans, and reviews the 11 patents that Transmeta asserted against Intel. [December 26, 2007]

• Figure 1: This figure, from Transmeta's 5,493,687 patent, illustrates a technique commonly used in microprocessors with hardware-level multithreading—multiple register banks, switchable for each thread context.

• Figure 2: This figure, from Transmeta's 6,226,733 patent, illustrates a method for speculatively calculating memory addresses in a microprocessor that has both memory paging and memory segmentation.

• Figure 3: This figure, from Transmeta's 7,100,061 patent, is a flow chart describing one way of dynamically adjusting the clock frequency and voltage of a microprocessor to save power.

• Sidebar: A chronological list of 24 Transmeta-related articles published in MPR since 1998. Many additional MPR articles have discussed Transmeta in relation to other microprocessor companies.

Altera's Nios II embedded-processor core is now a triple-threat contender. Thanks to a partnership with Synopsys, developers can license the 32-bit synthesizable processor for standard-cell implementations in ASICs as well as for FPGAs and structured ASICs. Previously, Nios II was restricted to Altera's FPGAs and HardCopy II structured ASICs, although Altera occasionally made special arrangements with favored customers. Now, anyone can license Nios II for a standard-cell design flow using industry-standard design tools, including the popular electronic-design automation (EDA) tools from Synopsys. [December 17, 2007]

• Figure 1: Altera's estimated performance of the Nios II/f processor when implemented as a standard-cell ASIC, as a structured ASIC, and in programmable logic.

• Table 1: Feature comparison of synthesizable 32-bit embedded-processor cores marketed for deployment in programmable-logic devices: Altera's Nios II/f (v7.2), ARM's Cortex-M1, Gaisler Research's LEON3, and the Xilinx MicroBlaze v7.0.

The RapidMind Multicore Development Platform requires programmers to rewrite the data-intensive portions of their code, and it also requires the target system to run a hardware-abstraction layer between the application program and the microprocessor. In return, RapidMind claims big benefits. Some tasks run five to ten times faster, and, in some cases, performance can scale faster than the rising number of processors. In addition, the parallel code is highly portable—programmers needn't rewrite it for each new multicore processor or multiprocessor system. Previously, RapidMind's platform worked only with IBM's Cell Broadband Engine (Cell BE) and the graphics processors from AMD/ATI and Nvidia. On November 5, RapidMind announced Multicore Development Platform v3.0, which targets the popular multicore x86 processors from AMD and Intel. [November 26, 2007]

• Figure 1: RapidMind's Multicore Development Platform v3.0.

• Figure 2: Parallel processing with RapidMind's platform.

• Figure 3: Comparison of C++ code before and after rewriting for RapidMind's Multicore Development Platform.

• Figure 4: Performance comparison of serial C++ code vs. RapidMind C++ code.

• Figure 5: Performance comparison of serial C++ code vs. RapidMind C++ code on x86 processors and an Nvidia GeForce 8800 GTX graphics card.

• Sidebar: RapidMind Wins HPCwire Awards at SC07 Conference

Xilinx is upgrading its MicroBlaze embedded-processor core again, this time adding an optional memory-management unit (MMU) that allows the 32-bit processor to run sophisticated operating systems supporting virtual memory. Developers can also substitute a simpler memory-protection unit (MPU) or omit supervised memory management altogether. MicroBlaze v7 has other improvements as well. New instructions provide faster floating-point performance and better I/O with coprocessors and custom logic. Xilinx has upgraded the CoreConnect interface to the latest CoreConnect Processor Local Bus (PLB) v4.6 specification, which provides faster links to on-chip peripherals. [November 13, 2007]

• Figure 1: Example SoC block diagram.

• Table 1: Sizes of three MicroBlaze v7 memory-management options.

• Table 2: MicroBlaze v6 versus MicroBlaze v7 performance.

• Table 3: Feature comparison of the Xilinx MicroBlaze v7, MicroBlaze v6, Altera Nios II, and ARM Cortex-M1 processor cores.

Customizable Atmel Processors (CAPs) invert the structured-ASIC formula to preserve the good aspects (design flexibility, rapid turnaround) while avoiding the bad aspects (complex design and verification, insufficient advantages over FPGAs and standard-cell ASICs). Instead of offering a blank slate of programmable metal encompassing nearly the whole chip, Atmel's CAPs are fundamentally ARM7- or ARM9-based microcontrollers with the usual integrated peripherals and I/O interfaces. Only about 10% to 20% of the chip is reserved for a metal-programmable block. By using this block to integrate additional peripherals, application-specific logic, or even multiple processor cores, customers can transform these off-the-shelf parts into the near equivalent of a custom ASIC. [October 29, 2007]

• Figure 1: Customizable Atmel Processor (CAP) die photo.

• Figure 2: Size comparison of Atmel's metal-programmable gates with standard-cell gates.

• Figure 3: CAP7 block diagram.

• Figure 4: Block diagram of Amulet Technologies' Graphical OS in Silicon technology for Atmel's CAP.

• Table 1: Soft macros available for CAPs.

ARC International has introduced five new members of the ARC Video Subsystem, a family of digital-video encoders and decoders. ARC licenses these subsystems to customers as soft intellectual property (IP) for integration in SoCs. The ARC Video Subsystem builds on the ARC VRaptor Media Architecture introduced in 2006. VRaptor, in turn, is based on an ARC 700 32-bit embedded-processor core augmented with instruction-set extensions, SIMD media processors, communication channels, special acceleration logic, and optimized software codecs for popular audio/video standards. Until now, ARC's preconfigured subsystems could handle video decoding but not the more challenging task of encoding. [October 15, 2007]

• Figure 1: ARC Video 417V block diagram.

• Table 1: Feature comparison of ARC's AV 402V, AV 404V, AV 406V, AV 407V, and AV 417V video subsystems.

• Table 2: A sampling of ARC's VRaptor Media Architecture.

• Table 3: ARC Video Subsystem performance.

• Sidebar: Future Directions: Mobile HD Video

• Sidebar: Hard-Wired Video Accelerators for ASICs

In July, Microprocessor Report described a new Power Architecture processor core that Intrinsity designed for AMCC using Fast14 dynamic logic. In that collaboration, Intrinsity played the role of a design house as well as an intellectual-property (IP) provider by designing a new Power-compatible microarchitecture to AMCC's specifications. Now, Intrinsity is playing a different role for ARM. Starting with an existing microarchitecture—ARM's Cortex-R4 embedded-processor core—Intrinsity is using Fast14 to transform the synthesizable model into a hard macrocell. The result is the ARM Cortex-R4X, the extreme-makeover edition of the Cortex-R4. [September 24, 2007]

• Figure 1: Power-performance envelopes of the ARM Cortex-R4 vs. the Cortex-R4X in a low-leakage 65nm CMOS fabrication process.

• Figure 2: ARM's sales estimates for various types of embedded systems in 2008.

• Figure 3: Comparison of a halt-propagate-generate cell implemented with Intrinsity's Fast14 1-of-N domino logic (NDL) and conventional static logic.

• Table 1: Feature comparison of the ARM Cortex-R4X, ARC 750D, MIPS 24KEc, MIPS 74K, and Tensilica Diamond 570T processors.

• Sidebar: ARM's Cortex-M1 for Low-Power Actel FPGAs

This month's issue of Microprocessor Report has an article about ARM's Cortex-R4X processor, a new hard-macro version of the previously released Cortex-R4 synthesizable core. What's special about this particular hard core is that it uses Intrinsity's Fast14 technology—a type of dynamic domino logic that has been demonstrated to significantly improve microprocessor performance. In our July issue, we reported on another interesting collaboration between Intrinsity and AMCC. With these projects, Intrinsity appears to be successfully redefining itself as an IP provider and design shop specializing in speed-optimized embedded-processor cores. [September 24, 2007]

If anyone still thinks multicore chips are merely the latest technology fad, banish such impure thoughts immediately. It has become clear that chip-level multiprocessing is the only visible path toward significantly higher performance, and every leading-edge processor company has a multicore strategy. The latest company to revamp its strategy is Freescale Semiconductor. Freescale is a good case study, because the company has been selling multicore chips—of a sort—since the mid-1990s. [August 27, 2007]

• Figure 1: Freescale's multicore platform block diagram.

XMOS Semiconductor is pushing a technology it calls "software-defined silicon." In this concept, a multicore array of general-purpose embedded-processor cores uses hardware multithreading to run the control software and application software under hard real-time constraints. At the same time, separate threads drive the chip's pins to emulate the required I/O interfaces—Ethernet, USB, UARTs, I2C, and so forth. This combination of multicore integration, deterministic multithreading, and software-defined I/O allows a general-purpose microprocessor to perform the functions of an SoC, but without custom acceleration hardware or dedicated I/O controllers. [August 6, 2007]

• Figure 1: Example XMOS C (XC) code for a UART transmit function.

• Figure 2: Developers can use standard C and C++ to write most software.

• Figure 3: Block diagram of a dual XCore design with XLink on-chip interconnect.

• Sidebar: Key People at XMOS Semiconductor

Last month I helped my brother purchase and set up his first new home computer in eight years. What should have been an easy job became a two-day ordeal that would be comical if it weren't such a sad commentary on today's PC industry. The villains include hardware manufacturers, software publishers, documentation writers, mass-market retailers, and corporate downsizers. All are clueless about serving their primary customers—ordinary users. And it seems to be getting worse, not better. [July 30, 2007]

AMCC and Intrinsity have joined forces to create an entirely new Power Architecture processor core. Code-named Titan, the 32-bit semicustom core relies heavily on Intrinsity's Fast14 logic to reach high clock speeds (up to 2.0GHz in 90nm bulk CMOS) while consuming remarkably little power (2.5W). In addition, Titan is part of a dual-core "processor complex" that supports coherent multiprocessing. If Titan succeeds, it will admit AMCC and Intrinsity to an exclusive club formerly limited to Freescale, IBM, and P.A. Semi—the only other companies creating original Power Architecture designs. [July 23, 2007]

• Figure 1: Comparing Fast-14 logic with conventional static logic.

• Figure 2: AMCC Titan pipeline diagram.

• Figure 3: AMCC Titan block diagram.

Cavium Networks is entering the mainstream storage-processor market with two families of Octeon chips based on the company's successful networking and communications processors. When the new storage processors debut late this year, they will bring the same high integration and programmability to networked storage systems that Cavium's existing processors have brought to routers, broadband-access devices, and many other networking products. The new Octeon Storage Services Processors will have two to twelve MIPS-compatible processor cores per chip, as much as 2MB of L2 cache per core, configurable I/O interfaces, and hardware acceleration for critical tasks. [July 16, 2007]

• Figure 1: Octeon SSP CN57xx block diagram.

• Figure 2: Octeon SSP sequential-read performance with iSCSI.

• Table 1: Feature comparison of Cavium's Octeon CN55xx and CN57xx Storage Services Processors.

Most companies fear commodity markets—those markets that subsist on razor-thin profit margins, providing sustenance only to the bottom-feeders. Typically, a new market opens with highly innovative products that command high profit margins. As more companies enter the fray, competition drives prices down. Eventually, the products become so plentiful and similar to each other that they become a nearly profitless commodity. That's Business 101. But I think much of the damage of commodity markets is self-inflicted. Lately I've been wondering if the spread of embedded-processor technology is partly to blame. [June 26, 2007]

Years ago, some crazy hot-rod mechanics crammed V8 engines into their classic Volkswagen Beetles. This hardware hack wasn't easy. The huge V8 transformed a cute Bug into a kludgy monstrosity. Freescale Semiconductor wants to bring a similar upgrade to embedded systems, only without the kludge quotient. So this week, Freescale is unveiling the first microcontroller family with pin-compatible 8- and 32-bit devices. Freescale's new Flexis-family MCUs for consumer and industrial applications will allow developers to pull an 8-bit chip out of a socket, replace it with a 32-bit part, update the firmware, reboot, and continue running the system as before—except with much more horsepower. [June 26, 2007]

• Figure 1: Flexis microcontroller block diagram.

• Table 1: Feature summary of Flexis 8- and 32-bit microcontrollers.

• Table 2: Flexis low-power modes.

At the recent Microprocessor Forum in San Jose, MIPS Technologies released power-consumption estimates and performance benchmarks for the new MIPS32 74K embedded-processor core. These preliminary numbers show the 74K running neck and neck with ARM's Cortex-A8. Microprocessor Report covered the MIPS 74K in detail shortly after its May 21 debut, but we overlooked some power-consumption estimates. In her Microprocessor Forum presentation, MIPS Engineering Director Vidya Rajagopalan showed the latest data for a 74Kc processor core synthesized for TSMC's 65nm GP process, using TSMC's standard-cell library and low-Vt transistors. [June 4, 2007]

• Figure 1: MIPS 74K vs. MIPS 24K performance.

• Table 1: Estimated MIPS 74Kc power consumption and performance.

Amazon.com grabbed headlines this month by announcing that it will sell music downloads unfettered by digital-rights management (DRM). Customers will be allowed to download and listen to the songs anywhere—on personal computers, portable music players, home sound systems, car stereos—and even burn copies on CDs. Amazon's announcement is trumpeted as a breakthrough for the music industry. That's funny. I remember enjoying the same freedom to make copies of music for personal use back in the analog vinyl-and-tape days. Even in the 1980s, when audio CDs introduced the world to digitized music, it was common to make cassette copies for the car and mix-tapes for parties. Amazon's "breakthrough" is more like a restoration of lost rights. [May 29, 2007]

It's so old, it's new again. In the 1990s, MIPS Technologies was at the forefront of RISC microprocessor design, introducing speedy workstation/server processors like the R10000 with deep superscalar pipelines and out-of-order execution. Now those features are reappearing in synthesizable embedded-processor cores. At last week's Microprocessor Forum in San Jose, California, MIPS showed that architectural acrobatics are making a comeback. MIPS introduced the MIPS32 74K, a new family of 32-bit synthesizable processor cores for demanding embedded applications. Among other tricks, the 74K uses two-way superscalar superpipelining and out-of-order execution—techniques once dismissed as too complex for lowly embedded processors. [May 29, 2007]

• Figure 1: MIPS32 74K pipeline diagram.

• Figure 2: MIPS32 74K processor core block diagram.

• Figure 3: Preliminary results of DSP benchmark tests on the MIPS 74K, 24KE, and 24K processors.

• Table 1: New instructions in the MIPS DSP Application-Specific Extension (ASE) Revision 2.

• Table 2: MIPS 74K performance characteristics after speed-optimized synthesis.

• Table 3: Feature comparison of the MIPS 74Kc, MIPS 74Kf, MIPS 34K, ARC 750D, ARM Cortex-A8, IBM Power 460S, and Tensilica Xtensa LX2 processor cores.

Vacuum tubes vanished from computers decades ago, but now vacuums are making a surprising comeback. IBM is introducing a new semiconductor-fabrication technique that creates "air gaps"—actually, tiny vacuum cavities—to replace the conventional insulation around copper wiring in integrated circuits. The preliminary results are even better than with the latest low-k solid dielectrics. Lower-k dielectrics reduce the capacitive coupling between adjacent wires, thereby improving current flow. Circuit designers can leverage lower capacitance to increase the chip's clock frequency, reduce the chip's power consumption, or choose some combination of those improvements. [May 21, 2007]

• Figure 1: This photograph, taken with an electron-beam microscope, shows the lattice-like atomic structure that emerges after IBM deposits its polymer material on a copper-metal layer.

• Figure 2: The drawing at the bottom of this figure illustrates the nanoscale holes that allow acids to create gaps in the solid dielectric material. Above are actual photographs of the tiny cavities.

• Figure 3: This electron-beam micrograph shows an oblique view of the metal layers in a chip fabricated with IBM's new air-gap technology.

• Figure 4: Additional electron-beam micrographs provide startling closeups of the tiny vacuum cavities.

With three keynote addresses, 20 technical presentations, and a full-day seminar on power efficiency—plus our traditional Tuesday-evening expo and party—Microprocessor Forum will celebrate its 19th anniversary this year. Dozens of companies are participating as presenters or sponsors. This event will be the only Microprocessor Forum in the U.S. in 2007, moving from its usual time in the fall to May 21-23 in San Jose, California. The only other scheduled forum is Microprocessor Forum Japan, on June 19-20 in Tokyo. [May 14, 2007]

• Photo 1: At last year's Microprocessor Forum, Intel's Dileep Bhandarkar delivered a well-received presentation on future power-management technology. Microprocessor Forum is the longest-running independent technical conference on all aspects of microprocessors.

• Photo 2: A Wi-Fi network allows conference attendees to download the latest versions of technical presentations and other materials. In-Stat will also make the materials available on USB flash drives.

• Photo 3: The traditional Tuesday-night Expo and Demo Showcase gives attendees a chance to huddle with industry celebrities while enjoying food and drink.

Multicore processors are leading the computer industry into uncharted territory. There might be entire minefields of hidden software bugs we haven't considered before. Two papers I've read on this subject are disturbing, especially because they warn that we have few alternatives. One paper is "The Problem With Threads," by Dr. Edward A. Lee, chairman of electrical engineering at the University of California at Berkeley. The other paper, also authored at that university, is "The Landscape of Parallel Computing Research: A View From Berkeley," by 11 experts on microprocessor architecture. It asserts that the only path toward significantly faster CPUs is chip multiprocessing, regardless of any consequential problems with threads. [April 30, 2007]

MIPS Technologies has negotiated a landmark licensing deal with STMicroelectronics that appears to resolve a long-running dispute with China over MIPS-like derivatives of the MIPS architecture...The Power.org consortium has formed technical subcommittees to resolve differences among Power Architecture microprocessors and processor cores...ARC International announced a surprising acquisition of Teja Technologies, and we suspect there's more to this deal than ARC disclosed in its press release...NXP Semiconductor (formerly Philips Semiconductors) showed some fascinating preliminary results of tests with the power-consumption benchmarks that EEMBC introduced last year...Innovasic Semiconductor, which specializes in satisfying demand for chips discontinued by other companies, wants to clone the Intel 386 processor, which Intel recently dropped from its product catalog. [April 23, 2007]

• Figure 1: ARC VRaptor block diagram.

• Figure 2: NXP Semiconductor measured power consumption of its LPC3180 microcontroller using EEMBC's automotive benchmark suite and EnergyBench.

• Figure 3: LPC3180 energy consumption per floating-point loop iteration, in microjoules.

For the first time, Freescale Semiconductor is making some of its Power Architecture embedded-processor cores generally available as licensable intellectual property (IP). Until now, only IBM has broadly licensed Power cores to chip developers. Freescale's move strengthens the Power Architecture as an alternative to widely licensed embedded-processor cores from ARM and others. The first Freescale cores released for licensing are four members of the 32-bit Power e200 family. All are fully synthesizable and portable to virtually any digital IC process. [April 2, 2007]

• Figure 1: Power e200z6 block diagram.

• Table 1: Feature comparison of Freescale's licensable Power e200z0, e200z1, e200z3, and e200z6 embedded-processor cores.

• Table 2: Feature comparison of six 32-bit Power Architecture embedded-processor cores available for licensing: the Freescale Power e200z6, IBM Power 460S, IBM Power 464-H90, IBM Power 464FP-H90, IBM Power 440, and IBM Power 405.

• Sidebar: Freescale Outsources Licensing to IPextreme

In a radical departure from past policy, ARM will allow licensees to synthesize some of its embedded-processor cores in FPGAs and is optimizing these cores for programmable-logic fabrics. Until now, with one exception, ARM has permitted licensees to synthesize ARM processors in FPGAs for development purposes only, not for product deployment. At the same time, ARM is announcing its first synthesizable processor core specially designed for FPGAs: the Cortex-M1. ARM says additional FPGA-optimized cores will follow. [March 19, 2007]

• Table 1: ARM Cortex-M1 instruction set.

• Table 2: ARM Cortex-M1 configuration options.

• Table 3: Feature comparison of seven 32-bit embedded-processor cores licensable for FPGA deployment: the ARM Cortex-M1, Altera Nios II/f, Altera Nios II/s, Altera Nios II/e, Gaisler Research LEON3, Xilinx MicroBlaze v5.0, and Xilinx MicroBlaze v4.0.

We are pleased to announce all the winners of our annual Microprocessor Report Analysts' Choice Awards for 2006. We have recognized seven companies: ARM, Ambric, Eutecus, Freescale Semiconductor, Handshake Solutions, Intel, and Planet82. One award was shared by two companies, ARM and Handshake Solutions. ARM and Intel each won two awards. Also in this month's editorial: a follow-up to our December 2006 editorial against paperless electronic voting. [February 26, 2007]

Microprocessor Report is presenting an MPR Analysts' Choice Award in the Innovation category to Eutecus, Inc., for designing a digital-imaging sensor-processor architecture that can capture and analyze up to 100,000 frames per second. The company's Cellular Visual Technology combines a massively parallel processor architecture with optimized image-processing software. Some implementations use an innovative semiconductor fabrication process to bond the image sensor directly onto the parallel-processor array, creating a multilayer chip. [February 26, 2007]

• Figure 1: An innovative semiconductor-fabrication process distributes thousands of indium bumps over the surfaces of the image-sensor and processor dies, bonding them together.

Microprocessor Report is presenting an MPR Analysts' Choice Award in the Innovation category to Ambric, an Oregon-based fabless semiconductor company founded in 2003. Bucking the usual trend, Ambric designed a new microprocessor architecture by first creating an innovative programming model, then fashioning an architecture capable of efficiently executing it. Ambric's Am2045 massively parallel processor crams 360 proprietary 32-bit RISC processors and 585KB of SRAM onto a single compact die. Maximum theoretical performance exceeds one trillion operations per second at 333MHz. [February 20, 2007]

• Figure 1: Partial Am2045 block diagram.

Microprocessor Report is presenting an MPR Analysts' Choice Award in the Innovation category to ARM and Handshake Solutions for the ARM996HS, the first commercially available 32-bit microprocessor core implemented in asynchronous (clockless) logic. ARM introduced the ground-breaking processor in early 2006. ARM's development partner was Netherlands-based Handshake Solutions, which worked closely with ARM to bring the unconventional technology to market. [February 20, 2007]

• Figure 1: Chart showing the much lower peak currents of the ARM996HS processor, which reduce electromagnetic emissions.

If a picture is worth a thousand words, what are 100,000 pictures per second worth? Plenty, to anyone who can design a digital-imaging system capable of achieving such spectacular frame rates. Applications include robotic vision, intelligent video surveillance, scientific analysis of momentary events, monitoring industrial processes, interactive games, and guidance systems for unmanned vehicles and missiles. With grants from the U.S. Missile Defense Agency and the Office of Naval Research, scientists from Hungary, Spain, and the U.S. founded Eutecus Inc. and developed Cellular Visual Technology. CVT combines a massively parallel processor architecture with optimized image-processing software. Some implementations use an innovative semiconductor fabrication process to bond the image sensor directly onto the parallel-processor array, creating a stacked multilayer chip. [February 12, 2007]

• Figure 1: Photo of Eutecus C-TON chip.

• Figure 2: Using an innovative manufacturing technique called 3D bump-bonding, Eutecus grafts an image-sensor die onto another die containing the massively parallel processor array.

• Figure 3: C-TON block diagram.

• Figure 4: At the abstract level, a Eutecus sensor-processor chip resembles a multilayer cake, with arrays of different components in each layer.

• Figure 5: The array processors can adjust the intensity of individual pixels, improving the photographic quality of the image.

• Figure 6: C-TON layout photo.

• Figure 7: Illustration of the saccadic jumps of human vision.

• Figure 8: Eutecus CVT technology allows developers to mimic the saccadic jumps of human vision by applying the processor array to different parts of a high-resolution image.

• Table 1: Performance measurements of basic image-processing tasks on a 100MHz C-TON processor.

Electronic voting machines are a classic example of botching a high-tech solution to a low-tech problem, thereby creating a new high-tech problem. It might be amusing if anything less than our democracy were at stake. U.S. election authorities are rushing into electronic voting without due diligence, without carefully considering the consequences, and without sufficient input from technical experts. Indeed, the situation is so appalling that I suspect almost any reader of Microprocessor Report could design better hardware and software than we have now. We don't really need electronic voting machines, but if we're forced to use them, let's at least do it right. [December 26, 2006]

On November 15, 1971, Intel introduced the world's first standard-part microprocessor, the 4004. It was a four-bit CPU with 2,250 transistors, and it ran at a clock speed of 740kHz. Intel manufactured the chip in a 10-micron PMOS process on two-inch silicon wafers and furnished the device in a 16-pin ceramic dual-in-line package. To celebrate this historic chip, Microprocessor Report covered the anniversary event at the Computer History Museum in Silicon Valley, which reunited codesigners Ted Hoff and Federico Faggin. Our coverage includes transcripts of their presentations, their responses during an audience question-and-answer session, our own technical analysis of the 4004, a block diagram of the processor, our newly reconstructed instruction-set table, and an analysis of how the 4004 transformed the computer industry. [December 18, 2006]

• Figure 1: Photo of Ted Hoff, coinventor of the Intel 4004, speaking at the 35th anniversary event at the Computer History Museum in Silicon Valley.

• Figure 2: Intel's first advertisement for the 4004 in late 1971.

• Figure 3: Photo of an original 4004 on a SIM-402 single-board development system that Intel sold to customers in the 1970s.

• Figure 4: Photo of Federico Faggin describing the 4004's layout during the 35th anniversary event at the Computer History Museum.

• Figure 5: Die photo of the 4004 with Federico Faggin's etched initials visible in the lower-right corner.

• Figure 6: Photo of the desktop calculator that Busicom built with the 4004 and other 4000-family chips.

• Figure 7: Intel's most widely reproduced photograph of the 4004 makes it appear the package has a cap made of wood, but it's actually a ceramic-and-gold package.

• Sidebar: Analyzing the Intel 4004
  • Figure: Microprocessor Report redrew this 4004 block diagram from vintage documentation, making minor modifications.

  • Table: Microprocessor Report reconstructed this 4004 instruction-set table by studying vintage documentation.

• Sidebar: How Microprocessors Upset the Computer Industry (by Don Alpert, Microprocessor Report Editorial Board)

Fending off ARM's latest punches, Tensilica is introducing two new versions of its 32-bit configurable-processor cores. The biggest improvements are error-correction codes (ECC) to protect caches and local memories, an optional memory-management unit (MMU) for both processors, and several new configuration options that can boost performance, save gates, and reduce power. The enhanced processors are the Xtensa 7 and Xtensa LX2. [December 4, 2006]

• Figure 1: Xtensa LX2 block diagram. Xtensa 7 has a similar microarchitecture.

• Figure 2: The Xtensa LX2 offers more I/O options than Xtensa 7 does.

• Table 1: Feature comparison of the new Tensilica Xtensa 7, existing Xtensa 6, new Xtensa LX2, and existing Xtensa LX processor cores.

Until now, forecasting the future of the Power Architecture (formerly PowerPC) required assembling a mosaic of individual roadmaps from different companies—some of which didn't even disclose roadmaps. That situation changed a few weeks ago, when the Power.org consortium released its first microprocessor roadmap consolidating the future plans of member companies. [November 27, 2006]

• Figure 1: These three roadmaps plot the future of 64-bit Power Architecture microprocessors, processor cores, and hybrid architectures.

• Figure 2: Power.org's roadmap for 32-bit chips.

• Figure 3: The Power.org roadmap for 32-bit processor cores has few surprises but does indicate that IBM intends to broaden its new Power 46x line.

• Figure 4: The Power.org roadmap for 32-bit hybrid/accelerated architectures.

• Sidebar: IBM's New Licensable Power Cores
  • Table 1: Feature comparison of the IBM Power 460S, Power 464-H90, Power 464FP-H90, Power 440, and Power 405 licensable processor cores.

Small improvements add up. At last month's Fall Microprocessor Forum, Xilinx unveiled an enhanced version of its licensable 32-bit processor core for FPGAs. Optimized for synthesis in next-generation Virtex-5 programmable-logic devices, the new MicroBlaze v5.00 processor uses deeper pipelining and higher clock speeds to boost integer performance by as much as 25% and floating-point performance by as much as 50% over the existing MicroBlaze v4.00 core. [November 13, 2006]

• Figure 1: Comparison of the MicroBlaze v5.00 five-stage pipeline with the MicroBlaze v4.00 (and earlier) three-stage pipeline.

• Figure 2: An example screen shot of the Xilinx Embedded Development Kit processor-configuration tool.

• Table 1: Comparison of synthesizing a typical MicroBlaze v5.00 configuration in Virtex-5 and Virtex-4 FPGAs.

• Table 2: Feature comparison of the Xilinx MicroBlaze v5.00, MicroBlaze v4.00, Altera Nios II/f, Nios II/s, and Nios II/e.

On average, there are 1.3 ARM processor cores per cellphone. And these days, it seems as if half the motorists on the road are yapping on their cellphones while driving. So, in a way, ARM already has a strong presence in the automotive market—though not exactly in the way the company desires. ARM wants to see more of its processors built into automobiles, not merely used in automobiles. Today, ARM's automotive design wins are based on older cores, such as the ARM7TDMI and ARM966. Newer designs need more processing power. So ARM has announced the Cortex-R4F specifically for the automotive market. [October 30, 2006]

• Figure 1: Six-year forecast of semiconductors in automotive systems.

• Figure 2: For efficiency, the Cortex-R4F integrates the FPU pipeline with the existing eight-stage integer pipeline.

• Figure 3: Partial superscalar pipelining allows the Cortex-R4F to dual-issue some pairs of integer and floating-point instructions.

• Figure 4: At synthesis time, developers can choose the granularity of error detection and correction in the Cortex-R4F.

• Table 1: This table shows the number of clock cycles required to perform some common single-precision floating-point operations on the new ARM Cortex-R4F, ARM's older VFP11 FPU, Freescale's Power e200 processor core, and Infineon's TriCore 1.3 processor core.

• Table 2: Small differences in configurations and synthesis scripts can have a great effect on the size and speed of the ARM Cortex-R4F, even in the same fabrication process.

• Table 3: Feature comparison of the ARM Cortex-R4F, ARM Cortex-R4, ARC 625D, ARC 750D, MIPS Technologies MIPS32 24Kf, and Tensilica Xtensa 6.

Relatively few people in the world know much about microprocessors—what they are, what they do, how they work. This ignorance may seem harmless. Merely learning how to use an electronic device is challenging enough. Why should ordinary folks get bogged down in low-level technical details that couldn't possibly matter to them? Unfortunately, as microprocessors become ubiquitous, knowing something about them is becoming not only desirable but necessary. Those who are familiar with microprocessors—including everyone who writes for this newsletter and everyone who reads it—should help educate the general public about an important technology that can seem as mysterious as string theory. [October 30, 2006]

Intel isn't out of the dark yet, but there's light at the end of the tunnel. And no, that glow isn't the laser beam of Intel's recent experiments with silicon photonics, which is a long-term beacon. Intel needs immediate results. Wisely, the company is returning to its traditional strengths: x86 processors manufactured with the world's best high-volume fabrication technology. It's a combination that competitors have found unbeatable. On September 26, Intel announced that quad-core server and desktop processors will begin shipping in November. Both product lines are months ahead of previously disclosed schedules. [October 16, 2006]

• Figure 1: Photo showing how Intel's first quad-core x86 processors package two dual-core dies in a multichip module (MCM), which Intel calls a multichip package (MCP).

At Fall Microprocessor Forum in San Jose, California, Ambric introduced the Am2045 massively parallel processor and architecture. This 117-million-transistor chip, fabricated in a modest 0.13-micron CMOS process, crams 360 proprietary 32-bit RISC processors and 585KB of SRAM onto a single compact die. Maximum theoretical performance exceeds one trillion operations per second (TOPS) at 333MHz. The Am2045 is designed to replace high-end embedded processors, DSPs, and FPGAs in applications that require fast general-purpose integer and digital-signal processing. [October 10, 2006]

Free link to this article in Adobe PDF format: Ambric's New Parallel Processor

• Figure 1: This conceptual diagram shows how software objects (essentially, subroutines or groups of related subroutines) run on multiple processor cores in Ambric's massively parallel array.

• Figure 2: Local channels that connect neighboring processor cores also synchronize the cores in Ambric's massively parallel architecture.

• Figure 3: Ambric's proprietary software-development tools are based on the Eclipse integrated development environment (IDE).

• Figure 4: A block of aStruct code, Ambric's textual source code for creating parallel structures of objects.

• Figure 5: This Java source code defines a class named PrimeGen. Objects instantiated from this class can test candidate integers to determine which are true prime numbers.

• Figure 6: Streaming RISC (SR) processor block diagram.

• Figure 7: Streaming RISC with DSP (SRD) processor block diagram.

• Figure 8: This block diagram shows a basic cluster of four processor cores, four local memories, and their associated interconnects and control structures.

• Figure 9: This block diagram shows one complete bric in the center, surrounded by parts of eight adjacent brics.

• Table 1: Benchmark results comparing the Am2045 with a high-end Texas Instruments DSP and a Xilinx Virtex-4 FPGA.

There are dozens, if not hundreds, of microprocessor architectures in the world. And Microprocessor Report covers new ones every year. With such abundance, it might seem daffy to use highly specialized 3D-graphics coprocessors for general-purpose number crunching. But the computational allure of GPUs is proving irresistible to the scientific community, chemical engineers, defense contractors, Wall Street financiers, and other heavy-duty math junkies. PeakStream, a Silicon Valley startup, has introduced new software and development tools that make GPUs relatively easy to program for data-intensive applications. [October 2, 2006]

• Figure 1: The PeakStream Platform includes a special virtual machine and a just-in-time (JIT) compiler. Programmers write application code in C++ and compile to a standard x86 binary, which embeds the function calls to PeakStream's math libraries.

• Figure 2: Two examples of C++ source code. Example A is typical sequential code without using any special function libraries. Example B uses PeakStream's math library.

• Table 1: Complete list of function calls in PeakStream's application programming interface (API).

To be fair, nobody should gloat over Intel's recent troubles. At one time or another, we've all been there, right? But let's be realistic. Many folks throughout the industry are not-so-secretly enjoying Intel's upheavals. They aren't trying very hard to hide their smirks and water-cooler jokes. It's the season of Intel's comeuppance, and it's been coming for a long, long time. But watch out—Intel has largely corrected its course and is now introducing some impressive new microprocessors. If anything, I expect Intel will be an even tougher competitor in the years to come. [September 25, 2006]

Our theme at In-Stat's Fall Microprocessor Forum is "Advances in Power Efficiency—Addressing the Global Challenge." All developers face the same problems, whether their design uses a tiny automotive microcontroller or a mighty supercomputer processor. Surprisingly, the solutions are largely the same, too, across the design spectrum. MPF will be held on October 9-11 at the Doubletree Hotel in San Jose, California. It will be our 18th annual fall conference, and it also marks In-Stat's 25th anniversary as a leading industry-analyst firm. To celebrate, we are reviving the famous MPF chip portfolio (every paid conference attendee gets a notebook with real microprocessor chips embedded in the cover), and we have arranged a stellar lineup of presenters. [August 28, 2006]

• Photo 1: A view of Spring Processor Forum last May.

• Photo 2: In-Stat will provide power outlets for notebook computers and a wireless network with access to forum presentations. Presentations will also be available on USB flash drives.

• Photo 3: The traditional Tuesday night expo and party is an opportunity to mingle with exhibitors and fellow attendees. The food and drinks are pretty good, too.

• Sidebar: Microprocessor Forums in Japan and Europe

After years of following different paths, the two key founders of the PowerPC architecture have renewed their historic collaboration. Working closely together again—now within the Power.org industry consortium—Freescale (the former semiconductor division of Motorola) and IBM are uniting their visions for the 15-year-old microprocessor architecture. Power.org has announced a new architectural definition that brings together features from both Freescale and IBM and lays the groundwork for future convergence. For the first time, all the documentation will be consolidated in a common format. And hereafter, the common architecture will be called the Power Architecture. "PowerPC" is relegated to existing products and historical references. [August 21, 2006]

• Figure 1: This new logo symbolizes the unified Power Architecture.

• Figure 2: This timeline shows the evolution of the PowerPC/Power Architecture since 1991.

• Figure 3: Power ISA 2.03 merges features from the Freescale and IBM modifications to the original PowerPC architecture, now known as PowerPC Classic.

• Figure 4: Power ISA 2.03 defines three privilege levels for software execution, but one level is optional.

• Figure 5: Power ISA 2.03 register files.

• Table 1: The PowerPC architecture is defined in a collection of books dating back to the original definition in 1991. Each book describes a different aspect of the architecture and has been revised over the past 15 years.

• Table 2: The PowerPC extension packages introduced by Motorola and Freescale are called auxiliary processing units (APU). Power ISA 2.03 makes the APUs official by renaming them "categories" and merging them into the new definition of the Power Architecture.

• Table 3: Comparison of memory-management features in PowerPC Classic 1.10 and Power ISA 2.03.

Only two weeks after AMD announced the sale of its Alchemy business unit to Raza Microelectronics (RMI), Intel announced that it's selling most of its XScale business unit to Marvell Technology Group. Both PC-processor giants are divesting embedded-processor businesses in the same month. What's going on? The obvious explanation is that AMD and Intel are refocusing on their core business—x86 processors for PCs. Certainly, both companies need to pay more attention to their foundations. But what makes sense for AMD doesn't necessarily make the same sense for Intel. [July 31, 2006]

MathStar calls its device architecture a field-programmable object array (FPOA). It consists of SRAM-based programmable logic, much like a conventional FPGA, but it's programmable at a higher level of abstraction. Instead of tinkering with gate arrays, designers work with a massively parallel array of preconfigured function units. Most of these units are identical ALUs or multiply-accumulate (MAC) units that can run autonomously. Others are register files shared by the ALUs and MACs. The first FPOA device has 400 of these 16-bit units woven together in a tightly coupled interconnect fabric. [July 24, 2006]

• Figure 1: Initially, MathStar has created three types of Silicon Objects: 16-bit ALUs, 16-bit multiply-accumulate (MAC) units, and 64-entry register files.

• Figure 2: MathStar MOA1400D block diagram.

• Figure 3: Diagrams of MathStar's on-chip interconnect fabric.

• Figure 4: MathStar's development flow for FPOAs differs in important respects from development for an FPGA.

• Figure 5: Block diagram of a multistream MPEG-2 decoder mapped onto the array of MathStar's 1.0GHz MOA1400D processor.

During a recent visit to China, Microprocessor Report learned that the country's leaders face a difficult technology decision: Which microprocessor architecture should they support in a coming wave of low-cost personal computers designed for the Chinese domestic market? The most obvious answer—the x86 architecture, already the world standard and the only platform running Microsoft Windows—isn't necessarily the best answer for China. This decision could significantly affect the direction of China's future economic growth. It's related to seemingly unrelated things, such as China's ambition for technology independence, a widening gap between rich and poor that threatens social stability, and mounting problems with urban sprawl and environmental pollution. [June 26, 2006]

• Photo 1: Worsening pollution in cities like Shanghai is making the Chinese question whether an economy based on heavy industry can support the kind of progress the country needs to make.

• Photo 2: In the former rural district of Pudong, across the river from central Shanghai, China has constructed a clone of Silicon Valley—complete with office parks, tree-lined boulevards, freeways, and exhibition halls.

• Photo 3: Weiwu Hu in his lab at the Institute for Computing Technology, part of the Chinese Academy of Sciences in Beijing.

• Photo 4: This is one prototype design of the $150 computer designed by the nonprofit One Laptop Per Child organization.

• Photo 5: This photo shows the Municator computer directly in front of a large video monitor, which displays the simplified GUI for launching application programs.

AMD is selling its Alchemy business unit to Raza Microelectronics (RMI), and we think it makes good sense for both companies—but only if the transfer includes a significant number of the original engineers. Without those alchemists, RMI will struggle to turn lead into gold. [June 26, 2006]

• Covering China in Microprocessor Report

• IBM's Blog for Game Developers

LSI Logic has introduced a new SoC-design platform called Zevio. It consists of hardware IP, software IP, and professional design services for consumer-electronics application processors. Zevio also has emulators and prototyping systems that allow customers to write software in parallel with hardware development. Zevio is compatible with several 32-bit processor cores from ARM and MIPS Technologies, as well as the ZSP family of 16-bit DSP cores. Customers can take the finished chip design to any independent foundry or use one of LSI Logic's affiliated foundries. [June 12, 2006]

• Figure 1: Chart showing that SoC-development costs are rising fast as fabrication technology moves to geometries below 0.18-micron.

• Figure 2: LSI Logic created a new SDRAM controller for the Zevio platform that runs twice as fast as the AMBA 2.0 AHB and fetches data in shorter memory bursts, reading only as much data as the AHB master needs.

• Figure 3: The Zevio SDRAM controller can write data to nonconsecutive memory addresses without rearbitrating the AHB.

• Figure 4: Block diagram of the geometry engine in the AHB-compatible graphics core for Zevio.

• Figure 5: Block diagram of LSI Logic's 3D rendering engine for Zevio.

• Figure 6: Block diagram of LSI Logic's 64-channel audio engine for Zevio.

The U.S. Patent and Trademark Office recently issued three new patents to Tensilica for its configurable-processor technology. They follow seven related patents issued from 2002 to 2005. In addition, the patent office has reaffirmed a key Tensilica patent issued in 2002 that was anonymously challenged a year later. As a result, Tensilica now holds an impressive portfolio of at least ten patents on configurable-processor technology. [May 30, 2006]

• Table 1: List of Tensilica's ten patents explicitly related to configurable-processor technology, including the patent numbers, titles, file dates, and issue dates.

If you attended our recent Spring Processor Forum in San Jose, thank you! I hope you're one of the attendees who won our drawing for an Apple iPod after submitting your feedback form. (You did submit a feedback form, right?) If you didn't attend SPF, we hope you'll tell us why and consider attending our Fall Microprocessor Forum in October. [May 30, 2006]

• Microprocessor Report is looking for a new editor in chief.

At Spring Processor Forum in San Jose, ARM revealed the first member of its Cortex-R family—the Cortex-R4, a synthesizable 32-bit processor core for deeply embedded applications. With this debut, ARM has now introduced initial members of all three of the new Cortex families announced in 2004. The Cortex-R4 duplicates the relatively high performance and relatively low power consumption of the existing ARM9, ARM10, and ARM11 families while incorporating the latest features of the ARMv7 architecture. [May 16, 2006]

• Figure 1: Growth projections for the Cortex-R4's target markets: automotive systems, hard-disk controllers, printers, home network gateways, and wireless modems.

• Figure 2: Cortex-R4 block diagram.

• Figure 3: Cortex-R4 pipeline diagram. At eight stages, the pipeline is one stage shorter than the ARM1156T2-S pipeline.

• Figure 4: Cortex-R4 synthesized layout. Excluding memories, the core size ranges from 180,000 to 220,000 gates.

• Figure 5: Looser timing for data transfers allows the Cortex-R4 to use slower, lower-power SRAM arrays for caches and tightly coupled memories.

• Table 1: The Cortex-R4 takes a small step toward user configurability by offering these options in prewritten scripts for the synthesis compiler.

• Table 2: ARM suggests configuring the Cortex-R4 in these ways for hard-disk controllers, chassis-level automotive systems, wireless modems, and imaging systems.

• Table 3: Using the configuration options in Table 1, ARM synthesized three different versions of the Cortex-R4 with Artisan cell libraries, targeting TSMC's generic 130nm and 90nm fabrication processes.

• Table 4: This comparison of two memory libraries from Artisan demonstrates why looser timing on the Cortex-R4's cache and TCM interfaces is a boon for developers.

• Table 5: Feature comparison of the ARM Cortex-R4, ARM1156T2-S, ARM946E-S, ARC International ARC 625D, ARC 750D, MIPS Technologies MIPS32 4KE, Tensilica Diamond 212GP, and Tensilica Diamond 570T.

In the digital age, embarrassing security breaches are becoming commonplace. A laptop computer with information about nearly 200,000 current and former Hewlett-Packard employees was stolen from Fidelity Investments. Flash-memory drives containing secret military intelligence were pilfered from a U.S. Army base in Afghanistan and openly sold in street bazaars. And, worst of all, Paris Hilton's cellphone address book was leaked on the Internet. IBM's Technology Collaboration Solutions Unit has an answer: SecureBlue, a new security technology for system-on-chip (SoC) devices. [May 8, 2006]

• Figure 1: IBM's new SecureBlue technology adapts the security features of this IBM 4758 PCI card into licensable IP for SoCs.

• Figure 2: SecureBlue block diagram.

On March 23, In-Stat and Microprocessor Report hosted our first-ever Microprocessor Forum in mainland China. It was a condensed one-day version of the three- or four-day events we've been hosting in Silicon Valley for more than 15 years. To help with logistics, we partnered with IDG China, an offspring of International Data Group, one of the first U.S. companies to establish a publishing business on the mainland. IDG's people worked closely with our Chinese analysts at In-Stat China, based in Beijing. As part of our China experiment, I traveled to Shanghai and Beijing to participate in our forum and meet with Chinese engineers and executives. [April 24, 2006]

Power consumption is the immovable object that is coercing irresistible forces like Intel, Apple, and IBM to find strategic detours. Searing wattage compelled Intel to abandon its pursuit of high clock frequencies and instead design PC processors with power-efficient cores. The same power-performance trends exerted so much gravity on Steve Jobs's reality-distortion field that Apple has abandoned PowerPC in favor of Intel's newly improved processors. And the very same immovable object persuaded IBM, Sony, and Toshiba to design the Cell Broadband Engine with a relatively simple PowerPC core surrounded by an array of power-efficient coprocessors. If the industry's heavyweights can't displace the immovable object of power consumption, but can only steer around it, what hope is there for the average line engineer designing an SoC? That's why our theme for Spring Processor Forum 2006 is power-efficient design. [April 24, 2006]

[Note: Access to this article doesn't require a subscriber password.]

If off-the-shelf network processors don't fit the bill, but designing a custom part is too costly or intimidating, Teja Technologies has a fresh alternative: Teja FP (FPGA Platform). It's a package of development tools, software, and hardware intellectual property (IP) that allows software engineers to build a packet processor in an FPGA without using a hardware description language (HDL) or fabricating custom silicon. With Teja FP, programmers can start with existing data-plane code written in ANSI C or write new code in that language. After profiling and analyzing the code, the next step is to partition the application. The most compute-intensive parts can execute in the FPGA's programmable-logic fabric, while other parts can run on soft processor cores synthesized in the fabric. [April 3, 2006]

• Table 1: Feature comparison of the Xilinx Virtex-4 FX programmable-logic devices with which Teja FP is compatible.

• Figure 1: A low-cost packet processor designed with Teja FP might use only two or three Xilinx MicroBlaze soft processor cores. Each MicroBlaze core is an engine in the packet pipeline.

• Figure 2: A high-performance packet processor designed with Teja FP requires several MicroBlaze processor cores. This example has nine cores.

• Figure 3: Hardware and software development with Teja FP is highly interactive. Using feedback from code profilers and actual execution in the target FPGA, developers can rapidly refine their design.

Tensilica has introduced six preconfigured versions of its 32-bit processor cores to suit an unusually broad range of embedded applications. Whereas the smallest configuration is suitable for deeply embedded microcontrollers in real-time systems, the largest configuration sets a new record for DSP benchmarks. [March 29, 2006]

• Table 1: Feature comparison of Tensilica's Diamond Series cores: the 108Mini, 212GP, 232L, 570T, 330HiFi, and 545CK.

• Table 2: EEMBC benchmark scores for the ARM1026EJ-S, ARM1136JF-S, and Tensilica Diamond 570T.

• Figure 1: Berkeley Design Technology DSP benchmark scores (BDTIsimMark2000) for the Tensilica Diamond 545CK, Ceva-X 1620, StarCore SC1400, and ARM1136.

Freescale Semiconductor's long-awaited decision to join Power.org strengthens the industry alliance and will help chart the course of the Power Architecture—just in time. Recent moves by ARM, Intel, MIPS Technologies, and Sun Microsystems are strengthening the competition, too. Power.org is an open industry consortium with more than 40 corporate members whose mission is to coordinate the future evolution of the Power Architecture, more commonly known as PowerPC. In 2004, when IBM formed Power.org, the most conspicuous absentee among the 15 founding members was Motorola spinoff Freescale. [March 6, 2006]

Microprocessor architects have explored many paths to high performance, including high clock frequencies, superscalar pipelines, application-specific extensions, very long instruction words (VLIW), and multicore processors. All those techniques and more are available in embedded-processor cores licensed as synthesizable intellectual property. Now MIPS Technologies is adding another option: the first licensable processor cores with hardware-enabled simultaneous multithreading. The new MIPS32 34K family consists of four 32-bit processor cores, all related to the MIPS32 24KE family. The key difference is pipelined multithreading. Instructions from as many as five different tasks can pass through the nine-stage pipeline of a 34K processor at the same time. [February 27, 2006]

• Figure 1: A graphical representation of simultaneous multithreading (SMT).

• Figure 2: By duplicating register files and other resources, a MIPS32 34K processor can run two operating systems and up to five thread contexts at the same time.

• Figure 3: MIPS32 34K pipeline diagram.

• Figure 4: Benchmarks indicate that the MIPS32 34K processor is 60% faster than a MIPS32 24KE processor when running packet-processing tests.

• Figure 5: This chart shows the number of gates required for two similarly configured 34K and 24KE processor cores—the same configurations MIPS used to obtain the benchmark results in Figure 4.

• Table 1: Feature comparison of the MIPS32 34Kc, 34kf, 34Kc Pro, and 34Kf Pro.

• Table 2: MIPS32 34K processors add eight new instructions to the MIPS32 Release 2 instruction-set architecture.

• Table 3: Feature comparison of the MIPS32 34K, MIPS32 24KE, ARC 700, ARM Cortex-A8, Tensilica Xtensa 6, and Tensilica Xtensa LX processor cores.

ARM has finally delivered the ARM996HS, the first commercially available 32-bit microprocessor core implemented in asynchronous (clockless) logic. ARM's development partner is Netherlands-based Handshake Solutions, which helped bring the unconventional technology to fruition. If the ARM996HS succeeds, it could spark a revolution in power-efficient processing that researchers envisioned even before microprocessors were invented. But the project still has risks. Several previous attempts to introduce a clockless 32-bit microprocessor have failed, and the ARM996HS remains unproved in silicon. [February 21, 2006]

• Figure 1: Power-consumption comparison of the ARM996HS and ARM968E-S.

• Figure 2: ARM996HS block diagram.

• Figure 3: The ARM996HS has a memory-protection unit that can segregate different regions of memory.

• Figure 4: Peak-current comparison of the ARM996HS and ARM968E-S.

• Table 1: Feature comparison of the ARM996HS, ARM968E-S, ARM966E-S, ARM946E-S, ARM926EJ-S, and ARM922T.

Cavium Networks is expanding its family of Octeon network/communications processors with chips that have one or two MIPS64 processor cores, instead of as many as 16 cores found in higher-end members of the family. But the new parts aren't simply chopped-down layouts. Their features, performance, power consumption, and prices vary according to their target applications, and they introduce some entirely new Octeon features, such as USB 2.0 and voice-over-IP (VoIP) interfaces. In all, Cavium has announced 10 new Octeon chips scheduled for sampling in 1Q06 and 2Q06. [February 6, 2006]

• Table 1: Differences of the Octeon CP, SCP, EXP, and NSP series.

• Table 2: Feature comparison of the Cavium Octeon CN3005 CP, CN3005 SCP, CN3010 CP, CN3010 SCP, CN3110 CP, CN3110 SCP, CN3110 NSP, CN3120 CP, CN3120 SCP, and CN3120 NSP.

• Figure 1: System block diagram of an Octeon-based 802.11n broadband wireless gateway with support for VoIP phones.

Deciding on our MPR Analysts' Choice Award for Best High-Performance Embedded Processor of 2005 wasn't easy. We evaluated several strong candidates before picking our winner: the Cell Broadband Engine, jointly designed by the STI alliance: Sony, Toshiba, and IBM Microelectronics. The Cell BE is destined for Sony's next-generation home videogame console, the PlayStation 3, scheduled for release later this year. [January 30, 2006]

Years from now, the industry may remember 2005 as the pivotal year when ARM began extending its reach from low power to high performance. In any event, we believe ARM's fastest processor to date—the Cortex-A8—deserves our MPR Analysts' Choice Award for Best Processor-IP Core of 2005. The Cortex-A8 is ARM's first superscalar processor core, and it's the first ARM processor capable of attaining clock frequencies in the gigahertz range. It's the biggest departure in processor design for ARM since the company was founded in 1990. [January 30, 2006]

This article contains our analysis of embedded-processor events in 2005 and speculation about what's to come in 2006 and beyond. We identify five broad trends in embedded processors. None of these trends actually started last year, but they gained momentum in 2005 and will be major forces in the future. For a concise summary of last year's developments, with links to related MPR articles, see the sidebar, "Embedded-Processor Highlights of 2005." [January 30, 2006]

• Figure 1: Block diagram of the Chinese Godson-2 microprocessor.

• Figure 2: Mercury Computer Systems introduced its Cell Technology Evaluation System in January 2006.

• Figure 3: Block diagram of Actel's Fusion FPGAs.

• Figure 4: Die photo of the triple-core processor that IBM designed for Microsoft's Xbox 360 videogame console.

• Figure 5: Block diagram of ARM's Cortex-A8 superscalar processor core.

• Figure 6: Die photo of the first eight-core XLR network processor from Raza Microelectronics.

• Sidebar: Embedded-Processor Highlights of 2005

Three things in life seem certain: death, taxes, and new microprocessor architectures. Unlike the first two things, new architectures aren't necessarily bad, but they are becoming even more expensive. The latest new microprocessor architecture to emerge is unconventional, massively parallel, and optimized for the narrow domain of high-definition digital video. Although Connex Technology's architecture is applicable to other purposes—such as pattern-matching filters in security processing—digital video is the largest potential market offering an opportunity for a profitable return on investment. [January 9, 2006]

• Figure 1: The Connex integral parallel architecture is based on a massively parallel array of processor cores known as processor elements (PEs). The first commercial chip has 1,024 PEs.

• Figure 2: PEs are arranged in a two-dimensional array, much like other massively parallel architectures, but Connex simplified the on-chip interconnect fabric by severely limiting the connections among the PEs.

• Figure 3: The Connex Machine can operate on 1,024 words of data simultaneously. These 16-bit words are arranged in a single-dimensional array or vector.

• Figure 4: Connex created a proprietary version of ANSI C, known as Connex Programming Language (CPL), that adds new vector datatypes and commands.

• Sidebar: The Key to Massive Parallelism: Think Small

Digital music distribution allows performing artists to circumvent the obstacles of expensive recording studios, greedy record companies, and corporate chain stores. Anyone can make their music available directly to the public. And it's understandable why listeners want their music in a pure digital format that liberates bits from atoms. Eliminating the physical media and packaging strips the music down to its essence: music. However, record-album covers were more than mere packaging. Are we sacrificing something worthwhile by distributing music as digital-audio files without visual artwork? [December 27, 2005]

• Photo 1: The Association's Birthday album, 1968.

• Photo 2: The Beatles' Sgt. Pepper's Lonely Hearts Club Band, 1967.

Just because ASIC and system-on-chip (SoC) projects are becoming prohibitively expensive for many developers doesn't mean there's less demand for custom chips. Product differentiation and integration still matter. Hence, the rush toward alternatives to full-custom silicon, such as FPGAs, structured ASICs, and reconfigurable processors. Actel's latest alternative is the Fusion Programmable System Chip (PSC)—a new breed of FPGA that can replace SoCs with a single off-the-shelf do-it-all chip. Fusion FPGAs combine reprogrammable logic with analog and digital peripherals, analog and digital I/O, SRAM, flash memory, and optional soft processor cores (a license-free ARM7TDMI-S or 8051). [December 19, 2005]

• Figure 1: Die photo of the Actel Fusion AFS600.

• Figure 2: Screen photo of Actel's CoreConsole, a new soft-IP integration tool for Fusion FPGAs.

• Figure 3: Screen photo of Actel's SmartGen, a new peripheral-configuration tool for Fusion FPGAs.

• Table 1: Feature comparison of the first four Fusion chips: the AFS090, AFS250, AFS600, and AFS1500.

In early November, Philips announced the TM3270, the first low-power TriMedia core for mobile applications. Other TriMedia cores deliver high performance but consume too much power for the new wave of portable consumer-electronics products. The TM3270 uses multiple techniques to cut power consumption and has new instructions and other features targeting digital video. It supports all the latest audio/video software codecs and can fully decode D1-resolution H.264 video streams while typically consuming less than 100mW. [December 5, 2005]

• Table 1: Feature comparison of the Philips TriMedia TM3270, TM3260, and TM5250 media-processor cores.

• Table 2: TM3270 power consumption while running an MP3 audio decoder on a 384Kb/s bitstream (44.1kHz stereo).

• Figure 1: A wide range of performance benchmarks comparing three different configurations of the TM3270 and the TM3260.

• Figure 2: Among the approximately 40 new instructions in the TM3270 is a collapsed-load operation that loads five bytes from memory and performs a linear interpolation before saving the four-byte result in a 32-bit register.

• Figure 3: Die photo and floor plan of the TM3270 core with a 64KB instruction cache and 128KB data cache.

At the recent Fall Processor Forum in San Jose, Tensilica previewed a high-performance video-decoder engine based on two Xtensa LX configurable-processor cores. Tensilica is preconfiguring the cores by customizing them with application-specific extensions, adding local memory and other intellectual property (IP), and licensing the whole synthesizable design as a drop-in module for SoCs needing video acceleration. [November 28, 2005]

• Figure 1: Block diagram of Tensilica's dual-core video-decoder engine. One Xtensa LX processor is configured as a stream processor and the other as a pixel processor.

• Table 1: Tensilica measured video performance on two simulated video-decoder engines: one using a pair of base-configuration Xtensa LX cores for the stream processor and pixel processor, and another using the same processors optimized with the new video extensions.

• Sidebar: Tensilica Introduces Xtensa 6 Processor Core
  • Feature and performance comparison of Tensilica's Xtensa V, Xtensa 6, and Xtensa LX configurable-processor cores.

Video is the next MP3, and any embedded processor competing for sockets in tomorrow's consumer gadgets must be able to handle digital video and audio processing. At Fall Processor Forum 2005, ARC International's chief architect, Nigel Topham, presented ARC's new SIMD extensions for digital video. These extensions are for the ARC 710D, 725D, and 750D—three preconfigured cores in the ARC 700 embedded-processor family. ARC will license the SIMD extensions as parts of larger extension packages released later this year. [November 21, 2005]

• Figure 1: ARC's new SIMD instructions can execute in a closely coupled mode or a decoupled mode, depending on the program's requirements.

• Figure 2: These two examples show how programmers can write the same code for closely coupled SIMD execution or decoupled SIMD execution.

• Figure 3: Pipeline diagram of the ARC 750D processor with SIMD extensions.

• Figure 4: Synthesized floorplan of an ARC 750D processor core with the ARCmedia Subsystem, which includes the new SIMD extensions.

• Table 1: List of 104 new instructions that ARC's SIMD extensions add to the ARCompact ISA.

• Table 2: ARC measured the digital-video performance of its new SIMD extensions by synthesizing an ARC 750D processor core in a Virtex-4 FPGA.

Gil Scott-Heron famously said the revolution will not be televised, but now it's looking like television is the revolution. TV is appearing everywhere, it's affecting everyone's lives, everyone is watching it, and it's watching everyone. In other revolutions, heads roll; in this one, heads talk. Into this maelstrom jumps Videantis, a startup based in Hannover, Germany. At Fall Processor Forum 2005, Videantis unveiled two synthesizable video-coprocessor modules based on the same proprietary processor core. Videantis wants to license the modules and optimized software to designers building programmable video chips for high-definition television (HDTV) and mobile consumer electronics. [November 7, 2005]

• Figure 1: Block diagram of the v-MP2 core.

• Figure 2: Block diagram of the single-core v-MP2000M video coprocessor module.

• Figure 3: Block diagram of the triple-core v-MP2000HD video coprocessor module.

• Table 1: Estimated performance of the v-MP2000M and v-MP2000HD when running popular video codecs.

Earlier this year, a Swiss startup, Innovative Silicon, announced a new embedded-memory technology called Z-RAM, because each one-transistor bit-cell requires zero capacitors. Z-RAM exploits an inherent electrical effect of silicon-on-insulator technology to temporarily store the bit-cell's binary state. In a technical presentation at Fall Processor Forum 2005, Innovative Silicon explained how Z-RAM works and made a strong argument that it's the logical alternative for embedding memory in future microprocessors. [October 25, 2005]

• Figure 1: Embedded memory already accounts for more than half the die area of typical microprocessors and SoCs, and it will soon overwhelm the silicon devoted to logic.

• Figure 2: Conventional embedded DRAM (eDRAM) requires a deep-trench capacitor structure in addition to the transistor for each bit-cell.

• Figure 3: How Z-RAM works. Innovative Silicon refers to positive charging as "impact ionization" and to negative charging as "hole removal."

• Figure 4: Detecting the difference between a stored 0 or 1 in a Z-RAM bit-cell is similar to sensing the value of a conventional DRAM bit-cell. At the top is a schematic of the cell.

• Figure 5: Z-RAM requires only one transistor, like conventional DRAM, but it doesn't need the deep-trench capacitor shown in Figure 2.

• Figure 6: This micrograph shows a one-transistor Z-RAM FinFET bit-cell fabricated for test purposes.

To celebrate the 40th anniversary of Moore's law, the Computer History Museum in Silicon Valley invited Dr. Gordon Moore and Dr. Carver Mead to talk about the law, reminisce about Moore's distinguished career in the semiconductor industry, and discuss other topics. On the evening of September 29, the museum's auditorium filled to capacity with an eager crowd of museum members and guests. Microprocessor Report recorded and transcribed this special event. [October 17, 2005]

• Photo: Dr. Gordon Moore

• Photo: Dr. Carver Mead

• Photo: Moore and Mead

In the latest attempt to lure embedded-systems designers away from 8- and 16-bit MCUs, Philips Semiconductor has introduced three new 32-bit MCUs with the ubiquitous ARM7TDMI processor core. The lowest-priced part—the LPC2101—has 8KB of on-chip flash memory and starts at only $1.47 in large volumes. That appears to be a new low price for flash-integrated ARM7 MCUs in this relatively high performance class (70MHz, 63 Dhrystone mips). The other two parts—the LPC2102 and LPC2103—have 16KB or 32KB of on-chip flash and cost $1.85 or $2.20, respectively. All three parts are stuffed with peripherals, timers, and other accoutrements of general-purpose MCUs. In addition, Philips has included features to address the shortcomings of previous 32-bit MCUs and to duplicate some advantages of 8- and 16-bit devices. [October 10, 2005]

• Figure 1: LPC210x block diagram. The only differences among the LPC2101, LPC2102, and LPC2103 are their amounts of internal flash memory (8KB, 16KB, or 32KB) and SRAM (2KB, 4KB, or 8KB).

• Table 1: Power-saving modes in the new LPC2101, LPC2102, and LPC2103.

• Table 2: Feature comparison of the new Philips LPC2101, LPC2102, and LPC2103; the Atmel AT91SAM7S32; and the Oki Semiconductor ML67Q406x and ML67Q500x.

Not since the days when RISC and VLIW challenged the CISC orthodoxy has there been such an upheaval in microprocessor design. Every major company in every major market—PCs, servers, and embedded systems—is converging on multicore processing. Microprocessor Report has provided front-line coverage of the multicore revolution since its beginnings in the 1990s. Now it's time to pull everything together for an event that covers all dimensions of multicore processing. The theme of Fall Processor Forum 2005, our 18th annual fall conference, will be "The Road to Multicore." FPF will offer technical presentations on new multicore processors, licensable intellectual property (IP) for multicore designs, on-chip interconnect technology for multicore chips, system software for multicore architectures, and software-development tools for parallel processing. [September 26, 2005]

Cavium Networks is as closely connected with network security as Linus in Peanuts is associated with his security blanket. Cavium gained fame with its award-winning Nitrox security coprocessors in 2002 and soon will begin shipping its Octeon NSP multicore network processors with integrated security engines. Now, Cavium is tossing aside part of its security blanket—for some chips, at least. Cavium's new Octeon EXP family is virtually identical to the Octeon NSP family, except that it discards the integrated cryptography engine and related features. Octeon EXP is for customers that don't need network security at this time or prefer using a separate security coprocessor. In addition, Cavium can freely export Octeon EXP chips to countries subject to U.S. government trade controls. [September 6, 2005]

• Table 1: Feature comparison of Cavium's Octeon EXP CN3630, EXP CN3830, EXP CN3840, EXP CN3850, EXP CN3860, and the Octeon NSP CN3xxx family.

• Table 2: Feature comparison of Cavium's Octeon EXP family with Broadcom's SiByte BCM12xx and BCM14xx processors, Freescale's PowerQUICC III MPC8641/D processors, PMC-Sierra's RM11200 processor, and Raza Microelectronics' XLR family.

(With Rich Belgard)

A showdown may be looming between ARC International and archrival Tensilica over who invented the software tools and methods for customizing synthesizable microprocessor cores. Both companies have won important U.S. patents for the technology, and ARC's latest patent appears both broad and strong. Whether or not ARC and Tensilica come to legal blows, their growing patent portfolios should worry other companies working in the expanding field of configurable processors. In general, Microprocessor Report agrees with ARC that U.S. patent 6,862,563 lays claim to key technology for automating the configuration of synthesizable processors and other soft intellectual property (IP). However, the complex language and convoluted history of the patent defy easy analysis and interpretation. [August 29, 2005]

• Figure 1: ARC's processor-configuration tool, now called the ARChitect Processor Configurator, runs on a PC or a Sun workstation. It has an easy graphical user interface that allows chip designers to rapidly customize an ARC processor core by choosing predefined options.

• Figure 2: In this excerpt from Figure 1, ARChitect indicates how the user has configured an ARC 700 processor core.

• Figure 3: Tensilica's processor-configuration tool underwent major changes last year. The predefined configuration options for the Xtensa LX processor now appear in Tensilica's integrated development environment (IDE), called Xplorer, which runs on the customer's desktop workstation.

• Figure 4: ARC's '563 patent has dozens of flowcharts like this one, showing how a processor-configuration program accepts user input to customize the synthesizable core.

• Figure 5: To eliminate any possible doubt about what constitutes a computer, ARC's patent describes the required components and illustrates them with this figure.

• Figure 6: This example of creating a custom instruction in Tensilica Instruction Extension (TIE) language is from Tensilica's website. It explicitly promotes TIE as a higher-level alternative to standard design languages like Verilog and VHDL.

As design costs soar like housing prices, ASIC alternatives are multiplying like Realtors. Actel—a second-tier FPGA vendor, behind market leaders Xilinx and Altera—is proving to be unusually creative at exploiting this opportunity. Actel has announced a technology called Fusion that, for the first time, can integrate mixed-signal logic with an embedded-processor core, flash memory, and SRAM in the same programmable-logic device. With Fusion, a single FPGA could perform some or all of the analog- and digital-processing functions in an embedded system. [August 15, 2005]

• Figure 1: Fusion block diagram. Fusion will integrate hard-wired analog peripherals with hard and soft intellectual-property (IP) cores in an FPGA. A soft embedded-processor core is optional. Tying everything together is the Fusion backbone, which consists of a multidrop bus and microsequencer implemented in programmable logic.

Beyond the land of the rising sun is the rising Godson, a growing family of microprocessors designed and manufactured in China by Chinese engineers for the Chinese domestic market. Intended for low-cost desktop computers, servers, and embedded systems, these 32- and 64-bit chips are rapidly becoming as sophisticated as any designs in the world, falling short in performance only because Chinese fabrication technology lags behind the rest of the industry by two process generations. Microprocessor Report recently interviewed Godson's chief architect, Weiwu Hu, a professor at the Institute of Computing Technology in Beijing. Weiwu described the Godson-1 and Godson-2 in unprecedented detail and revealed some of his ambitions for the Godson-3. After analyzing this information, MPR believes the Chinese already are capable of designing world-class microprocessors, if they can gain access to world-class fabrication technology. [July 25, 2005]

• Figure 1: Godson-2 block diagram. China's most powerful microprocessor is patterned after the MIPS IV ISA and is similar to the MIPS Technologies R10000 processor introduced in 1995.

• Table 1: The Godson-2's instruction latencies are similar to those of other high-performance RISC processors.

• Figure 2: Godson-2 pipeline diagram. ICT lengthened the Godson-2 pipeline by two stages, compared with the Godson-1.

• Table 2: Feature comparison of the Godson-1, Godson-2, and three important MIPS processors: the R3000, R4000, and R10000.

• Sidebar: A Conversation With Godson's Father—Excerpts from our exclusive interview with Weiwu Hu, chief architect of the Godson-1 and Godson-2 and a professor at the Institute for Computing Technology, Chinese Academy of Sciences, Beijing.
  • Photo of Weiwu Hu

• Sidebar: China Likes the x86, Too—Even while the Chinese develop their own Godson microprocessors patterned after the MIPS architecture, they are also seeking ways to make x86-compatible processors for China's domestic market and possibly for export.

In the 10 years since Sun Microsystems introduced Java, the dragon of slow run-time performance has pretty much been slain by better virtual machines, faster microprocessors, and extensions like ARM's Jazelle. Today, Java is successfully running on millions of cellphones and other embedded systems. Now, ARM is taking up another challenge: reducing code bloat when compiling Java bytecode with just-in-time (JIT) compilers or static native compilers. ARM's solution is a new variation of Jazelle called Jazelle RCT (Run-time Compilation Target) that enhances the 16/32-bit Thumb-2 instruction set to assist JIT compilers and static native compilers. [July 11, 2005]

• Table 1: Jazelle RCT extends Thumb-2 with these new Thumb-2EE instructions in the ARMv7 architecture.

• Figure 1: At best, a static native compiler enhanced with Jazelle RCT generated executable code only 7% larger than the original Java bytecode, according to these ARM internal benchmark tests. At worst, the same compiler generated code 44% larger—still impressive, considering that most static compilers inflate Java bytecode to several times its original size.

• Figure 2: These code snippets from a Java program demonstrate how Jazelle RCT conserves memory.

• Table 2: ARM's internal benchmarking indicates that an ahead-of-time (AOT) Java compiler can limit code bloat without significantly hampering performance.

Until now, the fastest single-core embedded processor was arguably Freescale Semiconductor's PowerPC MPC7447A, which boasted the highest EEMBC benchmark scores of any microprocessor chip. (Some specially customized versions of configurable processor cores have achieved higher EEMBC scores in simulation.) To defend its high ground, Freescale has unveiled an even faster microprocessor, the MPC7448—previously announced but without vital details. As newly certified EEMBC scores show, the 1.7GHz MPC7448 easily beats the 1.42GHz MPC7447A. [July 5, 2005]

• Table 1: Freescale's new 1.7GHz MPC7448 is the world's fastest embedded microprocessor chip, according to the latest EEMBC benchmarks.

• Table 2: Feature comparison of the Freescale MPC7448, Freescale MPC7447A, Freescale MPC8641/D, AMCC PowerPC 440GX, Broadcom SiByte BCM1250, IBM PowerPC 750GX, and PMC-Sierra RM9000x2GL.

Elixent took the stage at Spring Processor Forum 2005 to prove that listening to customers isn't a lost art. Using feedback from early adopters of its massively parallel configurable-processor core, Elixent has introduced D-Fabrix v2.0, which significantly boosts performance without increasing the overall gate count. [June 27, 2005]

• Figure 1: D-Fabrix v1.0 added dynamic multiplexers to the switchboxes in the on-chip network fabric. The original Chess architecture that inspired D-Fabrix lacked these muxes.

• Figure 2: Benchmark tests comparing the simulated performance of a D-Fabrix v2.0 processor with the baseline performance of a D-Fabrix v1.0 processor of equal size.

• Sidebar: Elixent Wins Japanese Design Award

Silicon Hive's mission is to replace DSPs and hard-wired application-specific logic with programmable processors based on its unbelievably long instruction word (ULIW) architecture. OK, we're exaggerating—ULIW actually stands for ultralong instruction word. But with instruction words stretching as long as 918 bits, this architecture does seem almost unbelievable. Last month, at Spring Processor Forum 2005, Silicon Hive introduced two new ULIW processor cores, the Avispa-IM1 and Avispa-CH1. This time, the company is targeting pixel processing as well as wireless communications. [June 20, 2005]

• Figure 1: Silicon Hive's Avispa-IM1 processor core includes eight of the new Generic DSP processing and storage elements (PSE).

• Figure 2: The Avispa-CH1 has a second new type of function block, known as a Complex DSP PSE.

• Table 1: Comparison of Silicon Hive's four ULIW processor cores: the Avispa-IM1, Avispa-CH1, original Avispa, and Avispa+.

From ARM's hometown of Cambridge, England, comes a new licensable embedded-processor core—except it's not from ARM. It's from Cambridge Consultants, a 250-person engineering firm that's been around since 1960. For decades, this company has been designing electronic gadgets for customers all over the world, but it's a newcomer to selling 32-bit microprocessors. At last month's Spring Processor Forum, Cambridge Consultants presented the new 32-bit XAP3a. [June 13, 2005]

• Figure 1: Layout of XAP3 register files.

• Figure 2: XAP3a block diagram.

• Table 1: Comparison of the Cambridge Consultants XAP3a with ARC International's ARC 600, ARM's ARM7TDMI-S, the MIPS Technologies MIPS32 4KE, and Tensilica's Xtensa LX.

Editor's note: This is an edited version of the white paper that MIPS Technologies submitted with its presentation at Spring Processor Forum. Microprocessor Report has added a sidebar analyzing the new MIPS32 24KE processor family. The 24KE adds DSP extensions to the high-performance 24K family of synthesizable embedded-processor cores. [May 31, 2005]

• Figure 1: MIPS32 24K instruction pipeline.

• Figure 2: The execution-stage datapath in the 24KEc.

• Figure 3: Forwarding results of DSP instructions from general-purpose registers requires a second clock cycle.

• Figure 4: Result forwarding to the next instruction without a delay is possible for useful DSP sequences.

• Figure 5: The dot-product-accumulate instruction performs two multiplications and two additions, storing the results in the specified accumulator.

• Figure 6: The multiplier datapath supports dual-multiply operations and a repeat rate of one MAC per cycle.

• Figure 7: Minimal additional logic was added to support DSP multiply instructions.

• Figure 8: Comparing performance of the 24KEc with the 24Kc on eight signal-processing tasks.

• Table 1: Comparison of the 24KEc with the 24Kc to show the effects of DSP extensions on core clock frequency, gate count, and die area.

• Sidebar: MIPS 24KE: Better Late Than Never (by Tom R. Halfhill)
  • Table: Feature comparison of the MIPS 24KEc, 24KEf, 24KEc Pro, 24KEf Pro, 24Kc, 24Kf, 24Kc Pro, and 24Kf Pro embedded-processor cores.

For years, ARC International has considered adding an optional floating-point unit (FPU) to its 32-bit customizable processor cores, but it has always been deterred by the cost of the additional logic gates and power. A fully equipped FPU with its own pipeline and register file could double or triple the silicon area of a small embedded RISC processor. At last week's Spring Processor Forum, ARC unveiled FPX—Floating-Point eXtensions—which significantly improve on the performance of a software-emulation library while requiring fewer gates than a complete FPU. [May 23, 2005]

• Table 1: List of new FPX single- and double-precision floating-point instructions, with descriptions and execution latencies.

• Figure 1: Results of ARC's benchmark tests with a customer's GPS application using single-precision FPX instructions.

• Table 2: Comparison of floating-point options from ARC, ARM, MIPS Technologies, and Tensilica.

Only AMD and Intel share a greater rivalry than Altera and Xilinx. These companies are the Hatfields and McCoys of the semiconductor industry. While the world's leading PC-processor vendors are shotgunning each other with double-barreled cores and 64-bit extensions, the world's leading FPGA vendors are battling over who has the biggest programmable-logic chips, the coolest design-automation tools, and the best synthesizable processor cores. Altera fired the last shot by introducing Nios II at Embedded Processor Forum 2004. This week at Spring Processor Forum, Xilinx is blazing back with MicroBlaze v4.00, the newest version of its 32-bit RISC processor core for FPGAs. [May 17, 2005]

• Table 1: The tightly coupled FPU, a new option, adds only 10 instructions to the MicroBlaze v4.00 architecture, which is backward compatible with v3.00.

• Figure 1: MicroBlaze v4.00 block diagram.

• Table 2: Feature comparison of MicroBlaze v4.00, MicroBlaze v3.00, Altera's Nios II/f, Nios II/s, Nios II/e, ARC International's ARC 600, and Tensilica's Xtensa LX.

How to beat the high cost of living: design a new chip around bits and pieces of LEON, a freely licensable SPARC-compatible processor core from the European Space Agency. The finished RAID controller chip is now solving space problems of a different sort by bringing affordable network-attached storage (NAS) to home and small-business users. The new LEON-derived chip is the IT3107 network storage processor from Infrant Technologies, a four-year-old privately held company in Fremont, California. This is the second RAID controller Infrant has designed using parts of LEON1, a 32-bit processor core adhering to the SPARC V8 instruction-set architecture. The European Space Agency freely distributes a synthesizable VHDL model of LEON1 under a GNU license. [May 2, 2005]

• Figure 1: Infrant IT3107 block diagram.

• Figure 2: Infrant's ExpandaNAS system board for NAS subsystems includes the IT3107 dual-core processor.

It's not a conference exclusively for embedded processors any more, but embedded processors and cores will nevertheless make the biggest news at this year's Spring Processor Forum (formerly Embedded Processor Forum). Innovation is running wild in the embedded industry, and SPF 2005 will be a showcase for radical multicore designs, aggressive new DSPs, new embedded-processor architectures, and much more. The forum, sponsored by In-Stat (publisher of Microprocessor Report), will be held May 16–19 at the Doubletree Hotel in San Jose, California. [April 25, 2005]

Philips Semiconductor is only weeks away from receiving silicon samples of the first Nexperia media processor based on the TriMedia TM5250 processor core. The new high-performance chip—dubbed the Nexperia PNX1700 Connected Media Processor—is designed for streaming digital-media applications, such as video decoding for high-definition television (HDTV). The TM5250, code-named Spitfire, is a 32-bit synthesizable processor core based on the TriMedia VLIW architecture, which first appeared in 1994. [April 18, 2005]

• Figure 1: Philips Nexperia PNX1700 block diagram.

• Table 1: The new TM5250 processor core in the PNX1700 introduces nine new instructions to the TriMedia TMA3 instruction-set architecture.

• Table 2: Descriptions of audio and video codecs to be offered by Philips and third-party IP vendors when the PNX1700 media processor ships later this year.

ARM-based chips continue to gain strength in the fast-growing microcontroller market. At the recent Embedded Systems Conference, Actel announced FPGAs with specially optimized ARM7 processors encrypted in programmable logic; Oki Semiconductor unveiled the world's smallest ARM-based MCUs; and Royal Philips Electronics introduced the first ARM9-based MCUs fabricated in a 90nm CMOS process. All these milestones provide more reasons to upgrade from 8- or 16-bit MCUs to 32-bit ARM-based devices. [April 4, 2005]

• Figure 1: Actel's security technology allows developers to encrypt and embed their IP in a ProASIC3 FPGA alongside the embedded ARM7TDMI-S processor core.

• Figure 2: Oki Semiconductor uses a proprietary manufacturing and packaging process to redistribute pins over the entire mounting surface of its wafer-level chip-size package (WCSP).

• Figure 3: Philips LPC3000 block diagram. Is it an MCU or an SoC?

It's been 10 years since Motorola created the PowerQUICC family of communications processors by substituting PowerPC cores for the 68360 CPUs in the original QUICC family. Now, Motorola spinoff Freescale is again improving the family with additional auxiliary processors, on-chip peripherals, I/O interfaces, and networking accelerators. The new chips belong to the PowerQUICC II Pro series and are called the MPC8360E and MPC8358E. Freescale will also offer them without integrated security engines as the MPC8360 and MPC8358. [March 21, 2005]

• Figure 1: Block diagram of Freescale's PowerQUICC II Pro MPC8360E.

• Table 1: Comparison of the new QUICC Engines in the PowerQUICC II Pro MPC8360E and MPC8358E with the communications processor module (CPM) in existing PowerQUICC chips.

• Table 2: Feature comparison of the Freescale PowerQUICC II Pro MPC8360E, Freescale PowerQUICC II Pro MPC8358E, Freescale PowerQUICC II Pro MPC8349E, Freescale PowerQUICC III MPC8541E, AMD Alchemy Au1550, and Intel IXP465.

ARC International has introduced six embedded-processor cores based on its configurable ARC 600 and ARC 700 families. The "new" 32-bit synthesizable processors are actually preconfigured cores, optimized for embedded applications in the low-power and high-performance realms. Although chip designers can further customize the cores for specific applications, the ready-made configurations are intended to accelerate design projects and allow easier comparisons with competing processors. The six preconfigured cores are the ARC 605, 610D, 625D, 710D, 725D, and 750D. All but one (the 605) have DSP extensions. [March 14, 2005]

• Figure 1: Comparison of performance when executing a 256-point FFT on an ARC 6xx or 7xx processor core with ARC's standard DSP extensions, Advanced XY DSP extensions, and Advanced XY extensions with DSPlib function library.

• Table 1: Feature comparison of the ARC 605, ARC 610D, ARC 625D, ARC 710D, ARC 725D, ARC 750D, ARM946E-S, MIPS32-4KE, and Tensilica Xtensa LX.

• Sidebar: ARC Wins Key U.S. Patent

After two years of labor, the Embedded Microprocessor Benchmark Consortium (EEMBC) has delivered its largest new test suite since introducing its original benchmarks in 2000. Indeed, the new Digital Entertainment suite (DENbench) has more tests than all five suites of the EEMBC 1.0 benchmarks put together. In all, there are 69 new tests, though most are alternative datasets for a smaller number of basic tests. They are grouped into four smaller suites that are useful for a broad range of applications, from consumer electronics to secure communications and digital rights management (DRM). [February 22, 2005]

• Table 1: List of the minisuites and tests in the DENbench suite.

• Table 2: Peak signal-to-noise ratio measurements for MPEG encoding and decoding on four benchmarked processors: the AMD Geode NX1500, Analog Devices Blackfin ADSP-BF533, Freescale PowerPC MPC7447A, and IBM PowerPC 750GX.

• Figure 1: One MPEG encoding test uses radar images of this mysterious "face" on Mars, as seen by a Viking orbiter.

• Sidebar: Few Surprises In First DENbench Scores
  • Table: Aggregate scores in all four DENbench minisuites, plus the floating-point MPEG-2 encoding tests, for the AMD Geode NX1500, Analog Devices Blackfin ADSP-BF533, Freescale PowerPC MPC7447A, and IBM PowerPC 750GX.

  • Figure: Performance-per-megahertz comparison of the AMD Geode NX1500, Analog Devices Blackfin ADSP-BF533, Freescale PowerPC MPC7447A, and IBM PowerPC 750GX.

Cavium Networks made a name for itself with security processors—timely products for an insecure world. More recently, the company has been introducing communications processors with security engines, a subtle but strategic shift. By integrating both communications and security, a single chip can do the job of two. Before long, security acceleration will be as common as caches in all types of microprocessors. The latest Cavium chips are the Nitrox Soho CN220 and CN225 secure communications processors, which incorporate the GigaCipher security engine found in Cavium's discrete Nitrox security chips. [February 7, 2005]

• Figure 1: Block diagram of Cavium's Nitrox Soho CN225 secure communications processor.

• Table 1: Feature comparison of Cavium's Nitrox Soho CN220 and CN225, AMD's Alchemy Au1550, Freescale's PowerQuicc II Pro MPC8343E, Intel's XScale IXP465, and PMC-Sierra's MSP2020 Multiservice Processor.

PC processors boast the highest clock speeds. Server processors have the fattest caches. But unsung embedded processors are at the forefront of microprocessor evolution. While the PC market is agog at dual-core 64-bit processors, the embedded market already takes such chips for granted and will deliver processors with four, eight, and sixteen 64-bit cores this year. Only the need for power efficiency restrains embedded chips from matching the high clock frequencies of PC processors and the bloated transistor budgets of the biggest server processors. Our year-end review of high-performance embedded processors finds that innovation in this market continued to accelerate in 2004. We also name the nominees and winner of our Microprocessor Report Analysts' Choice Award for Best High-Performance Embedded Processor of 2004. [January 31, 2005]

• Sidebar: Best High-Performance Embedded Processor: Broadcom BCM1480

Greater performance, architectural enhancements, and improved design tools marked the progress of intellectual-property (IP) embedded-processor cores in 2004. Although the number of companies competing in this tight market remained static, one company booted its CEO, hired a new executive management team, and changed its strategy (again). Another company announced a mind-numbing barrage of new products and spent nearly a billion dollars on a binge of acquisitions. And the biggest competitor announced plans to greatly expand its licensing strategy. Here is an alphabetical review of the leading processor-IP companies—ARC International, ARM, IBM Microelectronics, MIPS Technologies, and Tensilica—and the most important news they made in 2004. We also name the nominees and winner of our Microprocessor Report Analysts' Choice Award for Best IP-Core Processor of 2004. [January 24, 2005]

• Sidebar: Best IP-Core Processor: Tensilica's Xtensa LX

No microprocessor since Intel's Merced has stirred as much curiosity as the Cell processor under development by IBM Microelectronics, Sony, and Toshiba. Partly it's because Cell is destined for Sony's much anticipated PlayStation 3 videogame console, due in 2006. But Cell isn't meant just for fun and games. It's also intended for professional graphics workstations and other computing devices, which makes people wonder what kind of magic will be bottled in the chips. Tantalizing details will trickle out in February, when IBM presents several papers about Cell at the International Solid-State Circuits Conference (ISSCC) in San Francisco. Until then, nothing beats a weighty 57-page patent issued to IBM, Sony, and Toshiba by the U.S. Patent and Trademark Office on October 29, 2004. Patent 6,809,734 describes the Cell architecture in detail, with 42 pages of illustrations. [January 3, 2005]

• Figure 1: This drawing from the '734 patent shows the way packages of program code and data, called software cells, can migrate among different Cell-based systems for distributed processing.

• Figure 2: A processor element (PE) is the basic building block of a Cell processor, as shown in this figure from the '734 patent.

• Figure 3: Inside look at an APU, the functional equivalent of a processor core, as shown by another figure from the '734 patent.

• Figure 4: The shared DRAM attached to each PE of a Cell processor is divided into protected regions of memory called sandboxes, as shown in this figure from the '734 patent.

• Figure 5: The Cell architecture's "software cells" have a complex format, as this figure from the '734 patent illustrates.

• Figure 6: This figure from the '734 patent illustrates the way a slower Cell processor (top) and a faster Cell processor (bottom) can allocate "time budgets" in their APUs to execute time-critical tasks in the same amount of real time.

Moore's law gets more attention all the time. Google finds 223,000 hits for the term on the Internet, remarkable for something as arcane as semiconductor chip manufacturing. People who can't tell a silicon wafer from a compact disc don't hesitate to name-drop Moore's law at business lunches and parties, usually in the context of whether Intel stock is a good buy. Not since a falling apple led Sir Isaac Newton to discover universal gravitation have so many people been so captivated by a scientific law. Yet Moore's law isn't really a law in the formal sense, and it isn't scientific. As we approach the 40th anniversary of Moore's law in 2005, it's time to set the record straight. [December 13, 2004]

• Figure 1: Intel's graph of Moore's law tracks the actual progress of Intel microprocessors, not the predicted path of the law.

• Table 1: Comparing three different versions of Moore's law to the actual transistor counts of Intel's latest microprocessors.

From its roots in the 1950s, asynchronous logic has captivated circuit designers who yearn to break the bonds of clock-timed logic and create free-running processors that work at their own pace. It's been done many times, in many different ways, but conventional synchronous technology is too entrenched. Now, ARM and Handshake Solutions (a line of business within Royal Philips Electronics in the Netherlands) think conditions are changing in favor of asynchronous logic. Handshake Solutions has been working closely with ARM to design a fully asynchronous ARM9 processor core that ARM will license commercially in 1Q05. It will be the first commercial asynchronous 32-bit microprocessor. [November 29, 2004]

• Figure 1: Infrared thermal photographs of actively powered hot spots in Handshake Solutions' 8-bit 80C51-compatible microcontroller and a conventional 80C51.

• Figure 2: Diagram of Handshake Solutions' four-phase single-rail asynchronous signaling.

• Figure 3: Example of Handshake Solutions' proprietary Haste language for designing asynchronous logic at the behavioral level.

• Sidebar: For More Information About Asynchronous Logic

CPU cores in embedded processors are multiplying like rabbits and sprinting even faster. Four of the six presentations in the high-performance embedded session at Fall Processor Forum (FPF) 2004 described impressive new multicore designs. One new product family integrates up to 16 cores on a single chip. Clock speeds are soaring to 1.8GHz and beyond. What's going on? Networking and telecommunications. Although some other embedded applications require high-performance processors, the growing demands of packet routing, control-plane processing, and wireless infrastructures are forcing chip vendors to push their designs farther than ever before. [October 25, 2004]

• Table 1: Feature comparison of 13 new high-performance embedded processors from AMCC, Broadcom, Cavium Networks, Faraday, Freescale, and PMC-Sierra.

• Figure 1: Block diagram of Freescale's PowerPC 440SPe storage I/O processor.

• Table 2: Feature comparison of Broadcom's new SiByte processors: the BCM1255, BCM 1280, BCM1455, and BCM1480.

• Figure 2: Block diagram of Broadcom's SiByte BCM12xx/14xx with two or four MIPS64 cores.

• Table 3: The trade-offs of using Faraday's NetComposer structured ASICs.

• Figure 3: Block diagram of Faraday's NetComposer-II (NC-II).

• Figure 4: Block diagram of Freescale's MPC8641D with dual PowerPC e600 cores.

• Figure 5: Block diagram of PMC-Sierra's RM11200 with dual MIPS64 cores.

Designing the world's fastest supercomputer by drawing inspiration from embedded processors seems like imitating a Vespa when building a Formula 1 racer. As we've seen in the last few years, however, embedded processors are blazing the trail for advanced design strategies. So perhaps it's no surprise that IBM Microelectronics would pattern a new supercomputer processor after an embedded system-on-chip (SoC), even to the point of recycling a five-year-old processor core previously found only in embedded parts. The new dual-core supercomputer processor springing forth from the embedded gene pool is called BlueGene/L. It's destined for an awesome supercomputer of the same name, which will harness the power of 65,536 processor chips containing 131,072 PowerPC processor cores. [October 11, 2004]

• Figure 1: Components of the BlueGene/L supercomputer for Lawrence Livermore National Laboratory.

• Figure 2: Block diagram of the BlueGene/L microprocessor, which is based on the PowerPC 440 processor core.

• Figure 3: Each BlueGene/L processor is a node in five independent networks.

• Table 1: Sizes and power consumption for various cell blocks in the BlueGene/L microprocessor.

Already a well-regarded vendor of security processors, Cavium Networks is moving in a bold new direction. The company's new Octeon family of networking processors integrates three important functions in a single chip: packet processing, content filtering, and security. To provide enough muscle for all that heavy lifting, at line rates up to 10Gb/s, Octeon chips will have as many as 16 MIPS-compatible 64-bit processor cores, augmented by numerous coprocessors. [October 5, 2004]

• Figure 1: Octeon block diagram.

• Table 1: Feature comparison of Cavium's Octeon family: the CN3420, CN3430, CN3840, and CN3860.

If two heads are better than one, microprocessors are about to become twice as smart. Dual-core x86 processors for PCs and servers are coming soon from AMD and Intel, along with their transition to the x86-64 architecture. It's the biggest step in x86 evolution since the migration from 16 bits to 32 bits during the 1980s. Meanwhile, high-performance embedded processors and digital signal processors (DSP) are evolving at an even faster rate. Networking chips with as many as 16 processor cores are making their debut, along with massively parallel processors that squeeze hundreds of cores onto a single chip. All that and more is happening at Fall Processor Forum (FPF), formerly known as Microprocessor Forum. FPF will be held October 4-6 at the Fairmont Hotel in San Jose, California. [September 20, 2004]

• Sidebar: Introducing Processor Forum Taiwan

Business analysts and investors are still debating whether ARM's whopping $913 million acquisition of Artisan Components makes financial sense, but from a technology standpoint, it launches ARM into a whole new realm. Among other things, it erases all doubt that ARM is becoming a start-to-finish provider of semiconductor intellectual property, not just a vendor of embedded microprocessor cores. [September 7, 2004]

Digging into the past of the x86 architecture is like archaeology: You can never be sure what you'll find, but it's often surprising. So it goes with the LAHF and SAHF instructions, which AMD originally dropped from the 64-bit AMD64 architecture, then restored after discovering some software still needs them. (See MPR 7/19/04, "A Tale of Two Instructions".) We reported that Intel first introduced LAHF and SAHF in the 16-bit 286 processor of 1982, mainly to speed up context switching for operating systems. So imagine our surprise when a sharp-eyed reader from Germany took issue with our version of the historical record. [September 7, 2004]

We live in a season of divisive partisan politics: endless bickering, blame games, finger pointing, strident propaganda, arguments over strategy, and embarrassing scandals. And that's just the politics of microprocessor benchmarking. This 10,000-word in-depth article analyzes the state of benchmarking for embedded processors, paying particular attention to the Embedded Microprocessor Benchmark Consortium (EEMBC) and a controversial newcomer, Synchromesh Computing's Embedded Processor Rating System (EPRS), also known as the AMD Performance-Power Ratings. [August 30, 2004]

• Table 1: The original EEMBC 1.0 benchmark suites, as introduced in 2000.

• Table 2: New or improved benchmark suites EEMBC has introduced since April 2000 or will introduce shortly, including the networking 2.0 suite, the Java 2 Micro Edition (J2ME) suite, the 8/16-bit microcontroller suites, and the digital entertainment suite.

• Table 3: Synchromesh Computing's EPRS benchmark suites.

• Figure 1: Synchromesh Computing published these benchmark results in its white paper written for AMD. VIA's 533MHz Samuel-2 processor is compared with AMD's Geode GX 466 and Geode GX 533 processors.

It's been a relatively quiet year for MIPS-compatible processors, but Toshiba is making waves with a new family of high-performance embedded processors based on an enhanced MIPS64 core. The first member of the family is the TX9956CXBG, which has Toshiba's new TX99/H4 64-bit core, jointly developed with MIPS Technologies. It's a step up from Toshiba's existing 64-bit MIPS processors, because the TX99/H4 is Toshiba's first MIPS64-compatible core with superscalar pipelines and clock speeds beyond 500MHz. It's also the first chip in its class, from any vendor, to be manufactured in a 90nm IC process. [July 26, 2004]

• Table 1: Feature comparison of Toshiba's new TX9956CXBG, Toshiba's existing TMPR4956CXBG, AMCC's PowerPC 440GX (recently acquired from IBM Microelectronics), IBM's PowerPC 750GX, Intrinsity's FastMath, Freescale's MPC7447A, and PMC-Sierra's RM7900.

Everyone has experienced the woe of cleaning out a closet and discarding something we needed later. Maybe it was something trivial, like a Pet Rock. Maybe it was something important, like a Pete Rose rookie card. Or maybe it was something both trivial and important, like the SAHF and LAHF instructions in the x86 microprocessor architecture. The strange story of the death and resurrection of these instructions is a classic example of the reason the x86 architecture has grown so complex over the past 26 years. [July 19, 2004]

• For More Information: Web links to AMD's five-volume set of AMD64 programmer's manuals, Intel's two-volume set of EM64T programmer's manuals, AMD's application note for the CPUID instruction, and Intel's application note for CPUID.

What's even faster and cheaper than outsourcing a design project to India? Answer: outsourcing it to a robot. Or, actually, to a new processor design tool that automatically generates application-specific custom instructions by analyzing software written in plain-Jane C/C++. Last week, Tensilica announced that its long-anticipated XPRES (Xtensa PRocessor Extension Synthesis) tool will ship in 3Q04. Microprocessor Report first covered XPRES after Tensilica disclosed the then-unnamed technology at Embedded Processor Forum 2003. [July 12, 2004]

• Figure 1: Screen shot of a dataflow graph generated by Tensilica's C/C++ compiler and profiler to identify hot spots that XPRES can optimize.

• Figure 2: Screen shot of an XPRES control panel.

• Figure 3: A graph generated by XPRES to show 1,830,796 possible Xtensa LX configurations for accelerating an XviD MPEG4 video encoder.

• Figure 4: Screen shot from Tensilica's Xtensa Xplorer development tool.

• Figure 5: Tensilica's XPRES design flow uses feedback-directed optimization to enhance both the configurable Xtensa LX processor and the software-development tools that drive the front end of the process.

FPGA vendor Altera took the stage at the recent Embedded Processor Forum to introduce Nios II, a second-generation family of 32-bit synthesizable RISC processors. All Nios II cores are intended primarily for integration in system-on-programmable-chip (SoPC) devices—essentially, SoCs in FPGAs. However, they are also suitable for structured ASICs and regular SoCs, especially as a migration path from FPGAs if production volumes climb. [June 28, 2004]

• Table 1: Feature comparison of the Nios II/f, Nios II/s, and Nios II/e.

• Table 2: The complete Nios II instruction set.

• Table 3: Feature comparison of the Nios II/f, Nios II/s, Nios II/e, ARC 600, Tensilica Xtensa LX, and Xilinx MicroBlaze processor cores.

• Figure 1: Block diagram of a user-defined custom instruction.

Challenging ARM in the embedded-processor market is as daunting as challenging Intel in the PC market: you're cruisin' for a bruisin'. No wonder ARC International wanted to delay revealing everything about its new ARC 700 processor core until a marketing plan was in place. As ARC recently disclosed at Embedded Processor Forum 2004, the ARC 700 has additional features that directly challenge ARM's most popular processor cores: it's the first ARC processor with a memory-management unit (MMU), translation lookaside buffer (TLB), precise exception model, and multiple privilege levels. That makes the ARC 700 the company's first processor capable of running Linux and other sophisticated embedded operating systems. [June 21, 2004]

• Table 1: Feature comparison of the ARC 700, ARC 600, ARM926EJ-S, ARM1156T2F-S, ARM1176JZF-S, ARM1136JF-S, MIPS 4KEc Pro, MIPS 24K Pro, Tensilica Xtensa V, and Tensilica Xtensa LX.

• Table 2: Nine new instructions in the ARC 700.

• Figure 1: Die-photo comparison of an ARC 700 synthesized for silicon area vs. an ARC 700 synthesized for clock frequency.

At Embedded Processor Forum 2004, Tensilica announced new versions of its configurable microprocessor core and optional DSP engine, which are licensed as soft intellectual property (IP). The new Xtensa LX is a major upgrade of Tensilica's existing configurable processor core, the Xtensa V. It tackles three challenges vexing today's CPU architects: the architectural limitations on compute efficiency, the bottlenecks on I/O bandwidth, and rising power consumption. For SoC developers, Xtensa LX preserves the advantages of a customizable CPU architecture while laying the groundwork for future development tools that will further automate the task of creating an optimized SoC design. [May 31, 2004]

• Figure 1: Block diagram of Xtensa LX bus architecture, showing the optional second load/store unit.

• Figure 2: Block diagram of configurable on-chip I/O ports created in Tensilica Extension Instruction (TIE) language.

• Figure 3: Diagram comparing the default five-stage pipeline with the optional seven-stage pipeline.

• Sidebar: How Tensilica Busted the Benchmarks

Two decades of deregulation have slashed the cost of long-distance phone calls to pennies a minute, but even pennies aren't free. Business and residential customers eager for lower-cost alternatives are eyeing voice-over-Internet-Protocol (VoIP) telephony, which piggybacks digitized voice packets onto existing Internet services. Although Freescale's new MSC711x-series DSPs are useful for any 16-bit fixed-point signal processing, they are especially suited for packet telephony. Two of the chips have Ethernet media-access controllers, and all have time-division multiplexers (TDM), DDR memory controllers, 32-channel DMA, and generous amounts of on-chip SRAM. [May 18, 2004]

• Figure 1: Block diagram of FreeScale's VoIP reference design, which uses four MSC711x-series StarCore chips on a "DSP farm card" to assist a PowerQuicc II MPC8260 communications processor.

• Figure 2: Block diagram of FreeScale's StarCore MSC7116 DSP; other members of the family are minor variations of this design.

• Table 1: Feature comparison of Freescale's MSC711x family: the MSC7110, MSC7112, MSC7113, MSC7115, and MSC7116. All are based on the same StarCore SC1400 synthesizable DSP core. Also included for comparison: the previously announced MSC8122, a more powerful DSP with four SC140 cores.

Freescale Semiconductor—the newborn spinoff from Motorola—has introduced a new PowerQuicc II Pro family of communications processors and two new members of the PowerQuicc III family. In all, there are eight new PowerQuicc chips. The most significant improvements over existing PowerQuicc processors are higher-performance CPU cores, faster memory systems, enhanced network interfaces, and integrated security engines for encrypting and decrypting data packets. [May 10, 2004]

• Figure 1: PowerQuicc II Pro MPC8349E block diagram.

• Table 1: Feature comparison of the Freescale PowerQuicc II Pro MPC8349E, MPC8347E, and MPC8343E; Freescale PowerQuicc III MPC8541E; Freescale PowerQuicc II MPC8272; AMD Alchemy Au1550; and Intel XScale IXP425.

• Sidebar: New PowerPC Cores Promise Higher Performance

IBM Microelectronics has announced some important steps toward making the PowerPC architecture more widely available as licensable intellectual property (IP) for custom chip designs. However, the much publicized "Power Everywhere" initiative still falls short of matching the flexible licensing models and customizing options from competing IP vendors. Among the announcements: IBM will consider licensing any Power or PowerPC core or chip implementation, although limitations apply; IBM will allow customers to freely download a synthesizable model of the PowerPC 440 for evaluation; and IBM plans to form an open committee to help steer the future evolution of Power/PowerPC, although IBM will retain control of the architecture. [April 26, 2004]

• Sidebar: AMCC Strikes a Big Deal for PowerPC

During the two-day conference portion of Embedded Processor Forum 2004—May 18–19, at the Fairmont Hotel in San Jose, California—new embedded processors, architectures, and synthesizable cores will be unveiled by Altera, AMD, ARM, Cradle, Emblaze, MobilEye, Motorola, PMC-Sierra, StarCore, Texas Instruments, Tensilica, Ultra Data, and VIA/Centaur. Almost all these presentations will be the first technical disclosures of their products. The new processors run the gamut from traditional RISC and CISC architectures to bold new designs optimized for communications, mobile multimedia, machine vision, and signal processing. [April 19, 2004]

AMD's Alchemy family of MIPS32-based embedded processors has a new member that integrates a security engine for encrypted communications. The new Au1550 supports Internet Protocol security (IPsec) and the Secure Sockets Layer (SSL) protocol for virtual private networks (VPN). The Au1550 is the fourth, and most advanced, member of the embedded-processor family that AMD gained by acquiring Alchemy Semiconductor in 2002. [April 5, 2004]

• Figure 1: Alchemy Au1550 block diagram.

• Table 1: Feature comparison of the Alchemy Au1550, Alchemy Au1500, Alchemy Au1100, Alchemy Au1000, Intel XScale IXP425, and Motorola PowerQuicc II MPC8272.

An independent analysis by MPR indicates that the 64-bit x86 architectures from AMD and Intel are almost identical. We compared all the new instructions, modified instructions, deleted instructions, and modifications to the register files. We also compared the memory-addressing schemes and many other architectural features, such as data-addressing modes, context-switching behavior, interrupt handling, and support for existing 16- and 32-bit x86 execution modes. In every case, we found that Intel has patterned its 64-bit x86 architecture after AMD64 in almost every detail. However, we also found a few differences that could make some software written for one 64-bit architecture incompatible with the other architecture. [March 29, 2004]

• Figure 1: The new x86-64 execution modes and their characteristics.

• Figure 2: Comparison of the 32- and 64-bit x86 register files.

• Table 1: New instructions in the 64-bit architectures from AMD and Intel.

• Table 2: Deleted or reassigned instructions in the 64-bit architectures from AMD and Intel.

• Table 3: Summary of similarities and differences between AMD64 and Intel's Extended-Memory 64 Technology (EM64T).

• Sidebar: Intel and AMD Manuals Sing Similar Tunes

Only weeks after ARM announced the acquisition of Triscend, Xilinx loosened ARM's grip with a higher bid and wrestled the small chip vendor away from ARM. The Xilinx deal is final, averting a further bidding war or the intercession of other suitors. As ARM had planned, Xilinx will absorb almost all 41 Triscend employees and phase out Triscend's corporate identity. [March 15, 2004]

Only a few months after introducing the ARC 600 configurable processor, ARC International has announced another new core: the ARC 700. But it's not an egregious exercise in instant obsolescence. The new(er) ARC processor is fully compatible with its still-available predecessor and is intended for customers willing to tolerate a larger core in return for higher performance. ARC claims the ARC 700 is the smallest 400MHz 32-bit RISC core available—one-third the size of an ARM11 when fabricated in a 0.13-micron IC process—with lower power consumption to boot. [March 8, 2004]

• Figure 1: ARC 700 pipeline/block diagram.

• Table 1: New instructions in the ARC 700.

• Sidebar: New CEO Brings Varied Background to ARC

Encouraged by the reception of its first ARM9-based processor in 2001, Cirrus Logic is rolling out 10 more chips with an ARM920T core. All are highly integrated system-on-chip (SoC) devices with impressive features and on-chip peripherals, but the feature creep isn't coming at a price—even the new high-end chip costs 37% less than Cirrus Logic's first ARM9 processor from three years ago. [March 1, 2004]

• Figure 1: Block diagram of Cirrus Logic's Maverick EP9315 processor.

• Table 1: Feature comparison of Cirrus Logic's EP9301, EP9303, EP9304, EP9305, EP9306, EP9307, EP9309, EP9310, EP9311, EP9312, and EP9315.

No more is ARM the "chipless chip company." ARM's surprise acquisition of Triscend, a microcontroller vendor in Silicon Valley, will make ARM a fabless semiconductor company for the first time—at least in a small way. However, the slight departure from ARM's traditional line of business is actually a strategic move intended to strengthen that business. ARM's goal is to seed the market for ARM-based 32-bit microcontrollers as the industry makes a transition from less powerful 8- and 16-bit chips. [February 17, 2004]

• Table 1: Feature comparison of the Triscend A7VL05, Triscend A7VE05, Triscend A7VC05, Triscend A7VT05, Atmel AT91FR40xx, Hynix HMS39C70x, Oki ML67Q500x, and Philips LPC2106.

This detailed year-in-review article examines the market for "extreme" processors and describes five such processors nominated for our 2003 Microprocessor Report Analysts' Choice Awards: the ClearSpeed CS301, Cradle ECE3400/MPE3400, Intrinsity FastMath, Elixent ET1, and Xelerated Xelerator X10q. [February 9, 2004]

• Figure 1: Block diagram of the ClearSpeed CS301.

• Figure 2: Block diagram of the Cradle ECE3400/MPE3400.

• Figure 3: Circuit diagram of an OR gate implemented with Intrinsity's Fast14 logic.

• Figure 4: Block diagram of the Elixent/Toshiba ET1.

• Figure 5: Block diagram of the Xelerated Xelerator X10q.

The Xelerated Xelerator X10q has been chosen for the Microprocessor Report Analysts' Choice Award as the Best Extreme Processor of 2003. The Xelerator X10q deserves the award for both its extreme design, even by the standards of extreme processors, and its focused design, which doesn't allow complexity to obscure its utility. Although massively parallel processors are becoming almost commonplace, the X10q steps forward with a massively pipelined architecture. This unusual approach is justified for a high-performance packet processor that performs repetitive tasks in serial fashion. [February 9, 2004]

• Figure 1: Diagram of the X10q's unique pipeline, which is more than 1,000 stages long.

This comprehensive year-in-review article examines the growing market for media processors and describes five such processors nominated for our 2003 Microprocessor Report Analysts' Choice Awards: Equator Technologies' BSP-15; Intel's MXP5800; Motorola's MRC6011; Philips Semiconductor's TriMedia TM5250; and Silicon Hive's Avispa+. [February 9, 2004]

• Figure 1: Block diagram of the Intel MXP5800.

• Figure 2: Block diagram of the Motorola MRC6011.

• Figure 3: Pipeline diagram of the Philips TriMedia TM5250.

• Figure 4: Conceptual diagram of Silicon Hive's feedback-driven automated processor-design tools.

• Sidebar: Media-Related Processors in 2003 (including numerous links to previous articles in Microprocessor Report)

The Philips TriMedia TM5250 has been chosen for the Microprocessor Report Analysts' Choice Award as the Best Media Processor of 2003. The TM5250 deserves the award for proving that smart design work can keep a 10-year-old media-processor architecture competitive against newer, more-extreme architectures without sacrificing software compatibility. [February 9, 2004]

• Table 1: EEMBC consumer-suite benchmark scores and Philips MediaStone benchmark scores for the Philips TM5250, Philips TM1300, Philips PNX1300, Tensilica Xtensa V, Tensilica Xtensa III, Motorola PowerPC MPC7447, ARC ARCtangent-A4, and Hitachi/SuperH SH-4.

ClearSpeed Technology has successfully tested early production samples of its CS301 floating-point coprocessor and is delivering small quantities to prospective customers. The massively parallel chip is hitting all its design targets for clock frequency (200MHz), power consumption (less than 2W), and peak floating-point performance (25.6 GFLOPS). [January 12, 2004]

• Figure 1: Screen shot of a math-intensive drug-simulation program from the University of Bristol, England, running on a PC with six ClearSpeed CS301 coprocessors.

ARM's latest synthesizable processor cores will introduce several eagerly anticipated features when they ship to licensees in the second quarter of the new year. Enhancements cover the gamut from security and power management to code compression and on-chip I/O. It's a significant growth spurt for the youthful ARM11 family, which will celebrate only its second birthday in 2004. [January 5, 2004]

• Table 1: Feature comparison of the ARM1156T2F-S, ARM1156T2-S, ARM1176JZF-S, ARM1176JZ-S, ARM1136JF-S, and ARM1136J-S.

Since its founding in 1997, Sonics has been gradually establishing its on-chip interconnect technology among important customers like Broadcom, Flextronics, Fujitsu, Hitachi, Hughes, Intel, NASA, NEC, Nokia, Samsung, Texas Instruments, and Toshiba. Last fall, TI licensed additional Sonics technology for its OMAP wireless-communication processors, and an industry-standards body adopted the core-interface protocol backed by Sonics. Sonics' latest product is SiliconBackplane III, a new version of its interconnect fabric. [December 22, 2003]

• Figure 1: Block diagram of the Sonics SiliconBackplane III, Synapse 3220, and MemMax on-chip interconnects.

ARC International was the first to license a customizable microprocessor core, but financial success has been elusive, and new competitors keep emerging. In a bid to regain the initiative, ARC has extensively revamped its product line. The most significant announcement is the ARC 600 processor core, a successor to the ARCtangent-A5, the company's two-year-old flagship product. ARC has also decided to offer preconfigured CPU cores for vertical applications, and the first example is an ARC 600 with new hardware extensions and software codecs designed for portable digital-audio products. [December 15, 2003]

• Figure 1: ARC 600 pipeline diagram.

• Figure 2: Screen shot of ARChitect 2, the improved version of ARC's graphical processor-configuration tool.

• Table 1: Instruction-set extensions for the ARC 600 Digital Audio Platform.

• Sidebar: New Leadership Tries to Revitalize ARC

Parallel lines never meet, but great minds think alike. Maybe that explains the convergence of parallel processors at this year's Microprocessor Forum and Embedded Processor Forum. The latest example is a configurable parallel-processing architecture from Silicon Hive, a Netherlands-based startup funded by Philips Electronics. Silicon Hive has created what it calls an ultralong instruction-word (ULIW) architecture—an apt description. With instruction words that stretch up to 768 bits long, each containing scores of operations, Silicon Hive's ULIW architecture surpasses every known VLIW machine. [December 1, 2003]

• Table 1: Comparison of Silicon Hive's Avispa and Avispa+ processor cores.

• Table 2: Benchmark data showing the efficiency of some common signal-processing algorithms running on simulations of the Avispa and Avispa+ cores.

• Figure 1: Block diagram of the configurable ULIW architecture.

• Figure 2: Screen shot of a profiling tool showing the efficiency of an FFT running on an Avispa processor.

• Figure 3: Diagram of Silicon Hive's feedback-driven configurable design system.

ClearSpeed, a U.K.-based startup, revealed a massively parallel CPU architecture at Microprocessor Forum 2003 that's intended to revive the market for floating-point coprocessors. ClearSpeed's strategy is to offer much higher floating-point performance at much lower power levels than general-purpose CPUs do, enabling designers to build faster embedded systems and accelerator cards for PCs, workstations, and servers. Instead of bottom-trawling for the mass market, though, ClearSpeed is fishing for customers willing to spend $975 per chip for 25.6 billion floating-point operations per second (GFLOPS). [November 17, 2003]

• Figure 1: Labeled die photo of ClearSpeed's CS301 chip.

• Figure 2: Block diagram of a processing element, one of 64 in the CS301.

• Figure 3: Block diagram of the CS301.

• Table 1: Informal FFT benchmarks comparing the CS301 to a Motorola PowerPC MPC7410 processor.

With an eye on the growing market for consumer electronics, Philips Semiconductors announced a new TriMedia 32-bit processor core at Microprocessor Forum 2003. The swifter core will debut next year in Philips media processors destined for personal video recorders, wireless networks, high-definition TVs, and other audio/video products. Unlike some previous TriMedia CPU cores, the new TM5250 won't be offered as licensable intellectual property (IP). Instead, the TM5250 will spawn a new generation of standard-part Nexperia media processors designed and manufactured by Philips. [November 3, 2003]

• Table 1: Comparing the new TM5250 to the Nexperia PNX1300 (formerly TriMedia TM1300).

• Table 2: EEMBC consumer-suite benchmark scores and Philips MediaStone benchmark scores for the Philips TM5250, Philips TM1300, Philips PNX1300, Tensilica Xtensa V, Tensilica Xtensa III, Motorola PowerPC MPC7447, ARC ARCtangent-A4, and Hitachi/SuperH SH-4.

• Figure 1: Pipeline diagrams for various TM5250 function units.

• Figure 2: Estimated MediaStone scores for the TM5250 at clock frequencies ranging from 300MHz to 900MHz.

• Photo: The TM5250 design team in Sunnyvale.

Some of Motorola's latest 3G mobile phones will use an enhanced StarCore DSP that the company revealed at Microprocessor Forum 2003. The new SC140e core has several advanced features not found in other StarCore DSPs, including a new memory subsystem and a user-level privilege mode. Motorola says the enhancements will eventually appear in a future architecture from StarCore LLC, a spinoff formed last year by Motorola, Infineon, and Agere (formerly Lucent). [October 20, 2003]

• Figure 1: StarCore SC140e block diagram.

• Figure 2: How the SC140e's new cache-locking scheme works.

• Photo: The SC140e main design team in Israel.

• Sidebar: StarCore LLC Offers Soft DSPs
  • Table: Comparing features of StarCore LLC's SP1201, SP1202, SP1203, SP1401, SP1402, and SP1403 synthesizable DSP cores.

If you want a Big Mac, go to McDonald's. If you want a big MAC, see PicoChip Design. The U.K.-based company is introducing the PC102, a massively parallel communications chip that contains 344 processors, including 260 with multiply-accumulate (MAC) units. PicoChip COO and chief architect Peter Claydon announced the PC102 at Microprocessor Forum 2003. [October 14, 2003]

• Table 1: Comparing features of PicoChip's PC101 and PC102.

• Figure 1: Programmers can specify signal paths by using a structural subset of VHDL.

Tensilica has introduced a new package of audio extensions and software codecs for its Xtensa V configurable microprocessor core. Known as the HiFi Audio Engine, the optional extensions include 54 new instructions that accelerate common algorithms for digital-audio encoding and decoding. Tensilica's target applications are portable MP3 players, automotive sound systems, TV set-top boxes, smart phones, and home entertainment systems. [September 29, 2003]

• Table 1: HiFi Audio Engine instruction mnemonics and descriptions.

• Table 2: HiFi Audio Engine registers.

ARC International is offering a new package of microprocessor extensions and security software that can improve the performance of common cryptographic algorithms by an order of magnitude or more. The package, called ARCprotect, includes new instructions, registers, and middleware as licensable intellectual property (IP) for the current ARCtangent-A5 and future ARC microprocessor cores. The extension instructions focus on the popular AES, DES, and 3DES (triple DES) encryption/decryption algorithms that are the foundation of many network-security protocols. [September 22, 2003]

• Table 1: The new ARCprotect instructions and registers.

Trying to ascend above the fray of 32-bit microcontrollers, Triscend is revising its line of ARM7-based field-configurable MCUs. New on-chip peripherals and features will make them more suitable for industrial applications—particularly for motor controllers. The new A7V05 family initially has four members, all with ARM7TDMI processor cores running as fast as 70MHz. They will supersede the company's current line of ARM7-based MCUs next year. [September 15, 2003]

• Table 1: Feature comparison of the new Triscend A7VL05, A7VE05, A7VC05, and A7VT05 microcontrollers.

• Figure 1: Block diagram of the Triscend A7VT05.

"Trusted computing" is such a hot topic that a dictionary editor recently asked MPR if she should include the term in the next edition she's compiling. Nothing validates a trend like the migration of technobabble to everyday language. To make designing secure embedded systems easier, ARM is adding new security extensions to the ARMv6 architecture. The new TrustZone extensions are relatively simple, consisting primarily of one new instruction, a new configuration bit, and an additional permission level that supplements the existing user and privileged modes. [August 25, 2003]

• Figure 1: Block diagram of an ARM-based system-on-chip processor with various blocks secured by TrustZone.

Among the most unusual microprocessors unveiled at Embedded Processor Forum 2003 was picoChip Design's new PC101, a massively parallel device that integrates 430 16-bit processors on a single die. Indeed, the PC101's resources are so abundant that, to some degree, they are expendable—the chip's internal bus fabric can bypass a few processors ruined by manufacturing defects. Designed for cellular-telephony and wireless-network base stations, the PC101 is the first implementation of picoChip's picoArray architecture. [July 28, 2003]

• Table 1: The PC101's long-instruction-word (LIW) format.

• Figure 1: Block diagram of a picoChip PC101 array processor.

• Figure 2: Block diagram of the picoArray, with example signal flows.

• Figure 3: Diagram of multiple picoArrays chained together.

• Photo: Peter Claydon, picoChip's CEO and chief architect of the picoArray architecture, describes the PC101 at Embedded Processor Forum.

• Equator Revs Media Processor: Equator Technologies unveiled a new member of its media-processor family at Embedded Processor Forum 2003, claiming the chip will deliver more signal-processing performance than any other VLIW architecture. The new processor, the BSP-16, is scheduled for production in 3Q04. [July 28, 2003]

Seeking a soft spot between a rock and a hard place, U.K.-based Elixent is introducing a massively parallel processor core that strives to combine the programmability of a general-purpose processor with the performance of a hard-wired ASIC. The goal: a more flexible system-on-chip (SoC) processor that consumes less power and adapts quickly to different tasks, amortizing the development costs of an SoC over multiple projects. [July 21, 2003]

• Photo: Elixent's Alan Marshall describes the D-Fabrix architecture at Embedded Processor Forum 2003.

• Figure 1: A basic "repeating block" in the D-Fabrix architecture.

• Figure 2: Higher-level block diagram of Toshiba's ET1 implementation.

• Table 1: Comparing the performance of a hypothetical D-Fabrix processor with a DSP when interpolating RGB pixels.

More frightening than any Halloween mask is the over–$1 million price tag on a deep-submicron mask set. No wonder everyone is looking for ways to exorcise the demon. Motorola's latest weapon is the MRC6011, a new chip that has a programmable RISC controller, internal peripherals, and six DSP cores, each with 16 function units. Designed primarily for wireless infrastructures, the MRC6011 is an off-the-shelf alternative to a costly ASIC project or a conventional DSP. [July 14, 2003]

• Photo: Motorola's Roman Robles describes the MRC6011 at Embedded Processor Forum.

• Figure 1: High-level MRC6011 block diagram.

• Figure 2: DSP core block diagram.

• Sidebar: Defining Reconfigurable Processing (by Nick Tredennick).

At Embedded Processor Forum 2003 last week, Tensilica unveiled an impressive addition to the tool chain for its Xtensa configurable-processor architecture. A new code-analysis and hardware-generation tool—so new it doesn't have a catchy name—automatically creates processor extensions that accelerate critical functions in C/C++ source code. Custom extensions can include new instructions, registers, and function units. In minutes, the tool can evaluate thousands of possible extensions and sort them by performance (clock cycles) and efficiency (gate count). When a developer selects the optimal design for the target application, the tool automatically generates the extension in Tensilica's proprietary hardware design language and integrates it with the Xtensa processor core, ready for logic synthesis. [June 23, 2003]

• Photo: Tensilica's Dror Maydan, director of software development, presenting at EPF2003.

• Figure 1: Screen shot of Tensilica's graphical tool for selecting critical functions of C/C++ programs to optimize.

• Figure 2: Screen shot of the tool's performance/efficiency analysis chart.

• Table 1: Eleven variations of automatically generated custom extensions with their estimated gate counts, software speedups, and acceleration techniques.

• Table 2: Example algorithms accelerated with custom extensions, their speedup factors, the number of possible configurations evaluated, elapsed time for evaluations, and before-and-after code-size data.

• Sidebar: Xtensa Xplorer Unites Tool Chain
  • Figure: Screen shot of Xtensa Xplorer's Pipeline Viewer.

  • Figure: Screen shot of the Cache Xplorer.

Intel is mapping an ambitious strategy to virtually eliminate the hardware cost of wireless integration by making digital radios inexpensive enough to build into almost any chip. Two thrusts of the so-called Radio Free Intel initiative are a new microprocessor architecture and better radio integration with mainstream fabrication technology. The first goal is to create multiband communications processors that can automatically reconfigure themselves on the fly for different wireless standards. The other goal is to integrate a wireless-baseband processor and analog front end on a single CMOS chip—without the extra costs of external components, exotic semiconductors, or additional processing steps during fabrication. [June 9, 2003]

• Figure 1: Block diagram of Intel's prototype reconfigurable communications architecture.

• Josh Fisher Wins Eckert-Mauchly Award: Joseph "Josh" Fisher, a Hewlett-Packard senior fellow, will receive the prestigious Eckert-Mauchly Award this week at the International Symposium on Computer Architecture in San Diego, California. Fisher is winning the award for his pioneering work on VLIW. [June 9, 2003]

• Tensilica Patent Challenged: MPR has learned that an unknown party is asking the U.S. Patent and Trademark Office to reexamine one of the patents on configurable development tools issued last year to Tensilica. The challenge doesn't attempt to overturn the entire patent, but it does try to narrow the scope of about half the patent's broadest claims. The challenged patent is number 6,477,683, one of two issued to Tensilica on November 5, 2002. [June 2, 2003]

Eight-bit chips still account for 56% of microprocessor sales by volume and 40% of revenues, according to World Semiconductor Trade Statistics. Embedded-systems developers keep using these puny chips because they are unbeatably cheap, sip miniscule amounts of power, and are small enough to add a dab of silicon intelligence to almost anything large enough to see. Hoping to displace 8- and 16-bit chips with more-powerful (and more-profitable) devices, Philips Semiconductors is introducing a new line of ARM7-based 32-bit MCUs. To sweeten the bait, Philips is fabricating the new MCUs in a special 0.18-micron CMOS process that offers the option of embedded flash memory. [May 19, 2003]

• Table 1: Comparison of ARM7TDMI-based general-purpose microcontrollers with embedded flash, including the Philips LPC2104, Philips LPC2105, Philips LPC2106, Atmel AT91FR40xx series, Atmel AT91Fxxxxx series, Hynix HMS39C70x series, Oki ML67Q400x series, and Oki ML67Q500x series.

Intel's newest microprocessor for mobile PCs is hardly out the door, but already the Intel Communications Group is promoting it as a high-performance embedded processor for networking. Intel is also sketching a roadmap for future chip sets that will improve the differentiation between its embedded and PC/server platforms. The "new" embedded processor is the Pentium M, formerly known as Banias, which Intel introduced in March as part of the Centrino mobile PC platform. Intel's intention is to sell the embedded Pentium M into high-performance communications-infrastructure applications, such as core routers, server blades, and network controllers. [May 12, 2003]

• Table 1: Comparison of the Intel Pentium M, LV Pentium M, LV Pentium III, VIA C3 E-Series, Transmeta Crusoe SE, IBM PowerPC 750FX, Motorola PowerPC MPC7457, PMC-Sierra RM9000x2, and Broadcom BCM1250.

• Table 2: Comparison of three Intel core-logic chipsets for the Pentium M: E7501, 855GM, and 855PM.

Small is good if you're a jockey, a designer dog, or a microprocessor chip. Ubicom (meaning "ubiquitous communications") is a company that definitely thinks small when it designs packet processors for wired and wireless systems. Its latest NPU is the IP3023, which requires only about 50% as much silicon and 10% as much memory as some competing chips. Ubicom designed the IP3023 for wireless access points, wireless LAN (WLAN) bridges, broadband modems, home routers, and other consumer or enterprise products that operate near the edge of a network. The company's goal is to slash the bill of materials (BOM) for those systems by offering an efficient packet processor that reduces or eliminates the need for off-chip memory and protocol-specific I/O chips. [April 21, 2003]

• Table 1: Comparison of Ubicom's IP3023, IP2022, and IP2012 chips.

• Table 2: IP3023 instruction set.

• Figure 1: IP3023 block diagram.

• Figure 2: IP3023 pipeline diagram.

• Figure 3: Scaled die photo of Broadcom's BCM4710 and die plot of Ubicom's IP3023 with major function blocks labeled.

IBM's long-awaited decision to openly license PowerPC cores will offer formidable new competition for ARM, MIPS Technologies, and other vendors of 32-bit microprocessor cores. It's not just that PowerPC is a popular, scalable architecture with a wealth of development tools and software. IBM's marketing muscle will give the company an instant presence in the intellectual property (IP) marketplace, and its rocklike stability makes it a safe haven for nervous customers in tough times. [March 31, 2003]

San Diego-based Octera is introducing Javalon-1, a synthesizable microprocessor core that natively executes Java bytecode instructions. Javalon-1 is the first member of a small family of cores that will have minor variations on the same basic design. Chip designers can use Javalon-1 as the basis for a self-sufficient microcontroller or as a slave to another microprocessor core on an SoC or ASIC. [March 17, 2003]

• Table 1: The Java bytecode instruction set.

• Figure 1: Javalon-1 block diagram.

• Photo: Octera's Javalon-1 design team.

MIPS Technologies is the latest company to endorse the concept of configurable processors. At Embedded Processor Forum 2002, MIPS introduced the M4K Pro synthesizable processor core, which allows customers to add application-specific instructions. More recently, MIPS announced that all soft processors in the Pro Series are user extendable, thanks to a technology MIPS refers to as CorExtend. Initial Pro Series cores, in addition to the M4K, are the 4KSd, 4KEp, 4KEm, and 4KEc. This article analyzes CorExtend and compares it with the configurable-processor technology from ARC International and Tensilica. [March 3, 2003]

• Table 1: Feature comparison of the MIPS M4K Pro, 4KEp Pro, 4KEm Pro, 4KEc Pro, 4KSd Pro, ARCtangent-A5, and Xtensa V processor cores.

• Figure 1: MIPS CorExtend instruction format.

• Figure 2: How a custom instruction can replace a whole loop of assembly code.

• Figure 3: The MIPS graphical configuration tool.

• Figure 4: Tensilica's Processor Generator configuration tool.

• Figure 5: ARC's ARChitect configuration tool.

• Chartered Seeks Lucrative Customers: Reeling from what it describes as the sharpest market decline in the history of the industry, Chartered Semiconductor plans to close its oldest fab and refocus on customers that need advanced fabrication processes. The Singapore-based company's goal is to increase its fab capacity for 0.18-micron and smaller processes from 15% in 2002 to 50% by the end of 2004, without expanding total capacity. [March 3, 2003]

Our year-end review covers five vendors whose 32-bit processor cores were nominated for a Microprocessor Report Analysts' Choice Award in the IP Core Processor category: ARC International (formerly ARC Cores), ARM Holdings, Improv Systems, MIPS Technologies, and Tensilica. The nominated cores are: ARC's ARCtangent-A5 with the ARCompact instruction-set architecture; ARM's ARM1026EJ-S and ARM1136JF-S; Improv Systems' Jazz DSP with Crescendo solution kit; MIPS' M4K Pro Series; and Tensilica's Xtensa V. The winner: ARM's ARM1136JF-S, the first ARM11 processor core. [February 18, 2003]

• Table 1: Feature comparison of the six nominated processor cores.

• Figure 1: EEMBC TeleMark out-of-the-box benchmark scores for the ARCtangent-A4, ARM1020E, Improv Jazz XT, Improv Jazz 2020, TriCore TC1M, Intrinsity FastMath, LSI ZSP500, MIPS-20Kc, Xtensa III, and Xtensa V processor cores.

• Figure 2: EEMBC TeleMark optimized benchmark scores for the ARCtangent-A4, Jazz XT, FastMath, LSI ZSP 500, Xtensa III, and Xtensa V processor cores.

• Figure 3: EEMBC ConsumerMark optimized benchmark scores for the ARCtangent-A4, TriMedia TM1300, Xtensa III, and Xtensa V processor cores.

• Sidebar: Important Embedded-IP Events of 2002

• Sidebar: ARCompact: An Elegant 16/32-Bit ISA

Intel claims it will be the first company to mass-produce microprocessors using extreme ultraviolet (EUV) lithography, a revolutionary new photomask technology. Pilot production is scheduled to begin with the 45nm fabrication process in 2007–2008, using tools and techniques now being refined. Mass production is scheduled to debut with the 32nm fabrication process in 2009. EUV lithography will enable a significant leap forward in the circuit density of chips, because the shorter-wavelength light allows stepper tools to draw features at least 10 times smaller than is possible with today's technology. [February 10, 2003]

• Figure 1: The progress of circuit feature sizes (Moore's law), lithography wavelengths, and lithography processes, 1989-2011.

• Figure 2: The progress of lithographic photomask technology, 1992-2005.

AMD's new alliance with IBM to jointly develop 65nm and 45nm fabrication technology should relieve some pressure on AMD in the race to keep up with Intel. It also raises the possibility that AMD will take the larger step of using IBM as a foundry for chip manufacturing—either instead of or in addition to outfitting its own 65nm and 45nm fabs. [January 27, 2003]

• Figure 1: AMD's technology roadmap.

With the debut of Intel's new Pentium M mobile-PC processor (code-named Banias) only months away, Transmeta is trying to expand the potential market for its competing x86-compatible chips. The company has announced a new line of Crusoe SE (Special Embedded) processors aimed at embedded systems that need to run x86 software with high performance and relatively low power consumption. [January 13, 2003]

• Table 1: Comparison of the basic specifications of Crusoe SE chips with Intel's low-power Pentium III embedded processors.

• Transmeta Shows New TM8000 Astro: Transmeta is showing customers first samples of its next-generation mobile PC processor, promising to deliver production quantities by 3Q03. Although Transmeta is withholding most architectural details about the new TM8000 Astro until it's closer to release, the company says the processor will offer higher performance and additional power-management features. [January 6, 2003]

IBM Microelectronics has successfully produced the first short-channel nMOS transistors using silicon germanium (SiGe) and strained silicon with a silicon-on-insulator (SOI) substrate. The test chips, which have thousands of operational transistors, pave the way for IBM to introduce a combination SOI/strained-silicon fabrication process with 65-nanometer (nm) lithography in 2005. The payoff will be higher clock frequencies or lower power consumption, depending on the chip designer's priorities. [December 30, 2002]

• Figure 1: At the base of IBM's experimental transistor are thin layers of strained silicon and silicon germanium on the wafer's silicon oxide substrate. The surrounding cobalt disilicide on the raised source/drain layer reduces source-to-drain resistance.

(With Rich Belgard)

Tensilica has been granted two U.S. patents for its system of automatically generating a custom microprocessor core and compatible software-development tools, and the company has 16 more patent applications pending. If archcompetitor ARC International is granted U.S. patents for dozens of similar applications now pending—in addition to the international patents it already holds—the result could be a legal minefield for any other companies that try to offer configurable-processor technology. [December 9, 2002]

• Earlier Configurable Processors: Close, But No Cigar: Neither ARC nor Tensilica invented the concepts of customizable microprocessors or customizable processors with compatible software-development tools. However, MPR has been unable to find previous examples that duplicate Tensilica's system.

• VLIW Pioneer Bob Rau Dies: Dr. Bob Rau, Hewlett-Packard Fellow, pioneer of VLIW architectures, and recipient of numerous awards, died of cancer at his home in Los Altos, California, on December 10. He was 51. Before joining HP in 1989, Rau cofounded Cydrome in 1984 and was chief architect of the Cydra-5 computer, one of the first VLIW systems. [December 30, 2002]

• IBM and Chartered Join Forces With Fabs: Fabrication technology and fabs are getting so expensive that even the biggest companies are forming alliances to share the burden. The latest linkup is between IBM, a leading innovator in chip technology, and Chartered Semiconductor Manufacturing, the world's third-largest independent chip foundry. Their open-ended multiyear agreement includes joint technology development and shared fab capacity. [December 16, 2002]

• China Unveils MIPS-like CPU: A research group sponsored by the Chinese government has developed a MIPS-like microprocessor and has licensed the design to a Chinese startup company. The Beijing-based startup, BLX IC Design Corp., is currently sampling the chip and plans to begin production in 1Q03. It will be China's first commercial 32-bit microprocessor. [December 2, 2002]

Intel has disclosed intriguing details about its future Banias mobile processor at recent industry conferences, including Microprocessor Forum 2002. In addition to describing some of the chip's power-saving techniques, Intel emphasizes that Banias is a comprehensive "mobile platform," not just a lower-power CPU. At launch in 1H03, the platform will include mobile processors at various speed grades, two core-logic system chip sets, and dual-band 802.11a/b wireless networking. [November 25, 2002]

• Photo: Mooly Eden, general manager of Intel's Israel Design Center, unveils new details about Banias's power-saving techniques at MPF 2002.

• Table 1: Intel modified some NAND gates in the cache logic to reduce static current leakage.

• Figure 1: The three-level branch predictor in Banias improves on the two-level dynamic branch prediction in Pentium III processors, which is believed to be the starting point for the Banias design.

Glenn Henry, the outspoken president of VIA Technologies' Centaur microprocessor division, described VIA's new C5XL processor and updated his product roadmap at the recent Microprocessor Forum 2002 in San Jose. The C5XL appears to achieve the impossible: it adds a deeper pipeline, Intel-compatible SSE extensions, a faster FPU, support for two-way multiprocessing, a more-efficient L2 cache, and other improvements while actually shrinking its size in the same fabrication process. [November 11, 2002]

• Photo: Glenn Henry presents the C5XL at MPF 2002.

• Table 1: Comparison of the new C5XL and existing C5N.

• Figure 1: VIA's processor roadmap 2002-2004.

• Figure 2: Benchmark results for the VIA C5XL, VIA C5N, Intel Pentium III Celeron, and Intel Pentium 4 Celeron with Business Winstone 2001, Quake 3 Demo 2, 3D WinMark 2000, and CPUmark99 on a low-end system with $40 graphics card.

• Figure 3: Benchmark results for the VIA C5XL, VIA C5N, Intel Pentium III Celeron, and Intel Pentium 4 Celeron with Business Winstone 2001, Quake 3 Demo 2, 3D WinMark 2000, and CPUmark99 on a lower-end system with integrated graphics.

IBM is sampling the PowerPC 405EP, the newest member of its popular 405 family of SoCs. Among other features, the 405EP adds a second 10–100Mb/s Ethernet controller for greater flexibility in small routers and wireless LAN access points. The 405EP is also intended for DSL/cable modems and other network-edge products. The new chip is based on the 405D4 embedded processor core, an evolution of the 405B3 core introduced with the first chip in this series, the 405GP. [November 11, 2002]

• Table 1: Comparison of the new PowerPC 405EP with the existing 405GP and 405GPr.

Rarely does a downsized product raise expectations for high performance. But by trimming down the awesome 64-bit Power4 server processor and adding AltiVec media extensions, IBM has created an impressive and affordable PowerPC chip for smaller servers, graphics workstations, and desktop computers. Nobody at IBM would confirm rumors that a leading customer for the PowerPC 970 is Apple—and Apple is even more tight-lipped. Nevertheless, the 970 is such an obvious improvement over today's Motorola G4-family PowerPC chips that it's hard to imagine Apple using anything else in its top-of-the-line desktop Macs and servers. [October 28, 2002]

• Table 1: Feature comparison of the IBM PowerPC 970, IBM Power4, Motorola G4+, Motorola G4, and IBM/Motorola G3.

• Figure 1: PowerPC 970 block diagram.

• Figure 2: PowerPC 970 pipeline diagram.

• Photo: IBM's Peter Sandon describes the PowerPC 970 at the recent Microprocessor Forum.

AMD and Intel have introduced faster versions of their Athlon XP and Celeron desktop processors, including the first Athlon with a 333MHz front-side bus and the first Celeron to reach 2GHz. The new Athlon XP 2800+ and 2700+ processors run at core clock frequencies of 2.25GHz and 2.17GHz, respectively, and are priced at $397 and $349. Samples are available now, but production parts won't ship until November—and then only in limited numbers. [October 16, 2002]

• Figure 1: AMD's core and front-side bus frequencies, 1999-2002.

• Figure 2: Intel's core and front-side bus frequencies, 1999-2002.

• Tensilica Adopts CoreConnect Bus: Tensilica has licensed IBM's CoreConnect on-chip bus and is introducing a bus bridge for its Xtensa V customizable processor. The bridge allows system-on-chip (SoC) developers to integrate CoreConnect-compatible intellectual property (IP) with Xtensa processor cores. [October 7, 2002]

Intel has introduced 11 new speed grades of its mobile processors, including a 2.2GHz Pentium 4-M that's 10% faster than the previous top-of-the-line 2.0GHz Pentium 4-M. Soon after Intel's announcement, seven PC vendors unveiled notebooks that use the new 2.2GHz speed champ. AMD quickly followed a week later by announcing two faster speed grades of the mobile Athlon XP: the 2000+ and 1900+, which run at 1.67GHz and 1.6GHz, respectively. They are shipping in notebook computers from Compaq and Fujitsu. [September 30, 2002]

• Table 1: Specifications for Intel's 11 new mobile PC processors.

• Figure 1: Intel's product line of mobile PC processors is closely tiered by clock frequency and price, but it has some sharp peaks and valleys because of microarchitectural differences and marketing strategies. Note the anomolies, such as two 1.33GHz processors priced at $134 and $508.

(With Max Baron)

Once available to only a few favored customers, Texas Instruments' dual-processor OMAP family is now represented by a standard product. (These days, TI rarely spells out OMAP, which stands for Open Multimedia Applications Platform.) The new OMAP5910 chip unites a slightly modified ARM9TDMI microprocessor core with a TMS320C55x DSP core plus a generous amount of on-chip memory and a host of useful peripherals. TI is offering the OMAP5910 for embedded applications that need real-time control processing and data-intensive signal processing. [September 23, 2002]

• Figure 1: OMAP5910 block diagram

Tensilica is shipping the fifth version of its customizable soft microprocessor core since the debut in 1999, adding new features and enhancing some existing ones. According to Tensilica's simulations, the new Xtensa V core should run at 350MHz (worst case) when fabricated in a 0.13-micron CMOS process. Tensilica says some Xtensa V configurations will run even faster and that improvements to the company's proprietary hardware-design language and C/C++ compiler can boost actual software performance by 50% over the Xtensa IV. [September 16, 2002]

• Figure 1: Xtensa V now supports external DMA requests through the processor interface (PIF) and variable-latency devices on the local-memory interface (XLMI).

• Wiggle Room In EEMBC's Simulated Benchmarks: Has the temperature in Hades plunged below 32ºF? Perhaps, judging by MPR's amazing discovery that a CPU vendor deflated its own EEMBC benchmark scores by 25% to offer a more realistic estimate of actual performance.
  • Figure: Certified EEMBC benchmark scores for the Xtensa V (at 260MHz, 285MHz, and 300MHz), ARCtangent-A4 (150MHz and 200MHz), and Motorola PowerPC MPC7455 (1GHz).

• SiS Chip Set Supports PC1066 RDRAM: Although the RDRAM bandwagon has few followers these days, Silicon Integrated Systems (SiS) hopes its new SiSR658 core-logic system chip set will attract customers looking for high-end memory performance. It's the first chip set that officially supports PC1066 Dual RDRAM, and it's the only RDRAM-capable Pentium 4 chip set from a company other than Intel. [September 9, 2002]

Intel's next-generation 90nm fabrication process will use strained silicon, a new technique that boosts circuit performance and is also under development at other companies. The technique should significantly increase the clock frequency and only slightly increase the manufacturing cost of Intel's Prescott Pentium 4 when it debuts in 2H03. Experiments at other companies—including Hitachi, IBM, and startup AmberWave Systems—have shown improvements ranging from 30% to 120% in electron mobility and transistor current flow (drain current). Intel is claiming a 10-20% increase in drive current. [September 3, 2002]

• Figure 1: Strained silicon improves electron mobility by stretching the atoms in the silicon layer further apart.

• Figure 2: Intel's new transistors have some of the smallest features in the industry.

• Table 1: In-Stat/MDR's estimates of gross die per wafer for the latest desktop processors from Intel and AMD, excluding defects.

• Table 2: Intel and AMD both have aggressive roadmaps for process shrinks, but they have different priorities for new technologies, such as strained silicon and SOI.

• Athlon XP Passes 2GHz: AMD has announced two faster speed grades of the Athlon XP processor: the 2600+ and 2400+. The model numbers are benchmarketing comparisons with Pentium 4 clock speeds that deliver similar application performance. Actual core frequencies of the new Athlon XP processors are 2.13GHz and 2.0GHz, marking the first time AMD has reached 2.0GHz. [August 26, 2002]

• Pentium 4 Reaches 2.8GHz: Intel is shipping four new Pentium 4 processors, including three faster models. The new top-of-the-line 2.8GHz Pentium 4 is 11% faster than the previous champion, the 2.53GHz Pentium 4. The other three new processors run at 2.66-, 2.6-, and 2.5GHz. All four processors have the same Northwood core as other recent Pentium 4 chips. [August 26, 2002]

NOTE: There's a two-year gap in articles between August 21, 2000 and August 26, 2002. Tom worked at ARC Cores from 2000 to 2002 before returning to Microprocessor Report.

LinkUp Systems Brushes Bluetooth
ARM-Based L7205 Is Enhanced for Short-Range Wireless Technology

LinkUp Systems is sampling an embedded processor that's "Bluetooth ready"—a pitch that sounds suspiciously like advertising stereo speakers as "digital ready." And indeed, LinkUp's new L7205 stops far short of integrating everything necessary to implement a Bluetooth radio transceiver without using additional components. But LinkUp says the USB interface and souped-up UARTs on the L7205 can nibble a few dollars off the cost of a typical Bluetooth implementation. [August 21, 2000]

• Figure 1: Block diagram of the LinkUp L7205.

• Table 1: Comparison of the LinkUp L7205, LinkUp L7200, Cirrus Logic EP7209, Cirrus Logic EP7211, and Cirrus Logic EP7212.

Depending on your point of view—and there seems to be no middle ground here—microprocessors that natively execute Java bytecodes are as palatable as latte or as loathsome as stained teeth. But in Sweden, where the spirit of neutrality still flourishes, a company called Imsys hasn't stopped trying to accommodate both sides by offering an embedded processor with rewritable microcode that natively runs Java or doesn't, as you please. Now Imsys is introducing an enhanced version of its GP1000 processor known as the Cjip. The most interesting new feature is that Imsys has developed an entirely new instruction set to supplement the Java instruction set, which has also been improved. The new instruction set, available as a microcode library, supports Forth or C and C++, using a Java-like stack architecture. [August 14, 2000]

• Figure 1: Cjip block diagram.

• Figure 2: Configuration of multiple register banks and on-chip stack memory in the Cjip.

• Figure 3: The Java platform (compatible with Java 2 Micro Edition) as implemented on the Cjip.

Java and real-time processing usually go together like coffee and ketchup. But a Silicon Valley startup, aJile Systems, has a new Java chip that handles interrupts in real time and doesn't need a third-party RTOS. It also allows embedded-system developers to write all their software in Java—even device drivers and other low-level code that normally would be written in C or assembly language. AJile's aJ-100 microprocessor is based on the 32-bit JEM2 Java chip developed by Rockwell-Collins. [August 7, 2000]

• Figure 1: aJ-100 processor-core block diagram.

• Figure 2: The Java runtime environment as implemented by the aJ-100.

• Figure 3: aJ-100 chip block diagram.

• Figure 4: Embedded CaffeineMark 3.0 results for the aJile aJ-100, Intel StrongARM SA-110, MIPS R4600, and Intel Pentium.

Merge a Corvette and a Cadillac and you'll get a Detroit disaster. Yet IBM has successfully created a similar hybrid by crossing a fast PowerPC 440 core with the luxury features of a highly integrated communications chip. The result is the PowerPC 440GP, which IBM disclosed last month at Embedded Processor Forum. The 440GP is the first chip to use the PowerPC 440 embedded-processor core and is the first implementation of Book E, the embedded PowerPC architecture defined by IBM and Motorola. It's also the first processor to have a 128-bit version of IBM's on-chip CoreConnect bus. [July 31, 2000]

• Figure 1: PowerPC 440GP block diagram.

• Figure 2: The results of IBM's simulations with 64-, 128-, and 256-bit CoreConnect buses on the PowerPC 440GP.

• Table 1: Comparison of the IBM 440GP, IBM 405GP, Hitachi SH7615, Infineon TriCore Harrier-XT, and the Motorola PowerQUICC MPC8260.

• Photo: Donald Senzig, senior PowerPC system engineer at IBM Microelectronics, describes the 440GP at Embedded Processor Forum.

• New Motorola PowerQUICC II Costs Less: Motorola has announced a PowerQUICC II processor that sacrifices a few features in return for a 25% lower price, offering cost-conscious customers yet another choice in the growing line of integrated networking chips. The new PowerQUICC II MPC8255 is designed for midsize routers, switches, access concentrators, wireless base stations, and other communications equipment. [July 24, 2000]

• Two New MIPS Cores From LSI Logic: LSI Logic is introducing a pair of new MIPS-compatible microprocessor cores for ASICs: the MiniRISC EZ4021 and the TinyRISC EZ4103. Both cores are available now in LSI's EasyMacro format—a physical implementation of the synthesizable models that includes a cache controller, MMU, bus-interface unit, EJTAG debugging, and other features. [July 24, 2000]
  • Figure 1: Die photo with floorplan overlay of the MiniRISC EZ4021 EasyMacro in LSI's 0.18-micron G12P process.

If you're not satisfied with any of the network processors (NPUs) that everyone from C-Port and IBM to Intel and Sitera has announced in recent months, Lexra has an alternative: license NetVortex and build your own. NetVortex is the first licensable microprocessor architecture designed for packet processing. Because it allows designers to integrate from 1 to 16 cores on a die, NetVortex is suitable for a wide range of applications—everything from home-network gateways at the low end to OC-192 core routers at the high end. [July 17, 2000]

• Figure 1: How NetVortex uses multiple register files to switch contexts among threads with zero-cycle delays.

• Figure 2: Block diagram of a hypothetical NetVortex-based NPU that integrates 12 cores for packet processing at OC-192 wire speed.

• Table 1: Description of 18 new instructions in the NetVortex architecture.

• Table 2: The number of clock cycles required for typical packet-processing tasks and the percentage of capacity those tasks would use in a hypothetical NetVortex NPU.

• Photo: L. Patrick Hays, CTO of Lexra, describes NetVortex at Embedded Processor Forum.

Four top-tier vendors at PC Expo announced their intention to make notebook computers based on Transmeta's Crusoe processors. Some of these systems will use a new version of Crusoe that has twice as much on-chip L2 cache. Transmeta has also revealed a two-year roadmap of processors with higher clock speeds, greater integration, lower power consumption, and new VLIW cores. [July 10, 2000]

• Figure 1: Transmeta's roadmap of future processors.

• Figure 2: A real-time trace that shows the power consumption of a Crusoe TM5400 processor while playing a DVD movie and launching another Windows application.

• Figure 3: This real-time power-consumption trace shows an Intel 500/600MHz mobile Pentium III processor running the ZD Media BatteryMark 3.0 program.

• Figure 4: Another real-time trace that shows a 500/600MHz mobile Pentium III processor playing a DVD movie in battery-optimized (500MHz) mode.

• Table 1: Comparison of Transmeta's present and future microprocessors.

• Table 2: Comparison of Transmeta's TM5400 and TM5600 Crusoe processors to Intel's 500/600MHz and 600/750MHz mobile Pentium III processors.

• Transmeta Explains LongRun: For the first time, Transmeta reveals the technical details of power management in the Crusoe TM5400 processor.
  • Figure: How Transmeta's LongRun power management changes the processor's voltage and frequency to match software demands.

  • Photo: Transmeta's Mark Fleischmann, director of low-power programs, explains LongRun at Embedded Processor Forum.

On June 12, unfazed by the burgeoning number of network processors (NPUs), SiByte disclosed the first details of its new SB-1 microprocessor core at Embedded Processor Forum. If the Silicon Valley startup can deliver what it promises—a 1GHz core that surpasses 2,000 Dhrystone mips while consuming only 2.5W—the SB-1 will push MIPS-based NPUs to new heights of power efficiency and performance. [June 26, 2000]

• Figure 1: Block diagram of SiByte's SB-1 four-issue superscalar core.

• Figure 2: The SB-1's deep ALU, FPU, and load/store pipelines.

• Figure 3: An example of an integrated NPU with multiple SB-1 cores and on-chip peripherals linked over the ZBbus.

• Table 1: Comparison of SiByte's SB-1 with the MIPS 20Kc, MIPS 5Kc, Lexra NetVortex, and IBM PowerPC 440 processor cores.

• IDT's RC32334 Integrates PCI: IDT's new Internetworking Products Division has announced its first chip, a 32-bit MIPS-compatible embedded processor with integrated PCI and SDRAM controllers. The 32334 is intended for low-cost network equipment, such as small-office routers, LAN switches, and home DSL gateways. [June 26, 2000]
  • Table 1: Comparison of IDT's RC32334 with QED's RM5720, IBM's 405GP, Hitachi's SH7751, and Motorola's MPC8240.

High-level synthesis tools and configurable CPU cores already bring some of the malleability of software to microprocessors. Now ARC Cores is taking the next step: CPU "plug-ins." The technical concept and business model for ARC's plug-ins will be familiar to users of PC software. In a similar fashion, ARC is encouraging intellectual-property providers and even its own customers to develop and sell extensions to ARC's configurable embedded-processor cores. [June 19, 2000]

• Figure 1: Generic bus structure of the ARC 3 synthesizable microprocessor core.

• Figure 2: Screen shot of ARChitect, ARC's graphical CPU-design tool.

Intel has introduced five embedded processors based on the same 0.18-micron Coppermine die found in most Pentium III and Celeron processors for the desktop and mobile markets. Actually, the embedded versions of the chips are identical to the desktop/mobile processors, but Intel guarantees longer availability (at least five years) and is signing up more third-party companies to support the parts with system software and development tools. Three of the new embedded processors are Pentium III designs, and two are Celeron designs. [June 12, 2000]

• Table 1: Feature comparison of the embedded Pentium III-733, Pentium III-700, Pentium III-500, Celeron-566, Celeron-400, and QED RM7000A.

Programmable network processors (NPUs) are the newest rage, and one of the latest examples is from Sitera, a four-year-old startup based in Longmont, Colo. Sitera recently began sampling a multiprocessor chip called the Prism IQ2000 and plans to start production in 4Q00. As with similar NPUs from C-Port, IBM, and Intel, the IQ2000 is intended to replace some of the dedicated ASICs found in routers, switches, and network-gateway devices. [May 29, 2000]

• Figure 1: System diagram of the IQ2000 in a router application.

• Figure 2: Block diagram of the IQ2000 network processor.

• Table 1: Feature comparison of three different versions of the IQ2000.

It's coming a year later than Motorola had hoped, but the CF5407—the first standard chip based on the ColdFire V4 core—is a significant improvement over the two-year-old CF5307. It delivers three times the raw performance, twice as many mips per megahertz, and nearly four times as many mips per watt. And the 5407 is almost pin compatible with the 5307, requiring only a lower Vcc supply (1.8V) and different clock inputs for its core, so developers can make boards that work with either chip. [May 15, 2000]

• Figure 1: CF5407 block diagram.

• Figure 2: CF5407 color die photo.

• Table 1: New and improved instructions in the ColdFire V4 instruction set.

• Table 2: Comparison of the CF5407 and CF5307.

• Table 3: Comparison of the Motorola CF5407, IDT 32364, National Semiconductor 486SXL, AMD 486DX5, and IBM PowerPC 403GCX.

Silicon Valley startup Massana has formed partnerships with two providers of embedded-processor cores—Lexra and Xemics—to offer integrated cores that combine CPUs with Massana's DSPs. The deal with Lexra teams the FILU-200 soft DSP with Lexra's LX4180, a 32-bit soft CPU core that's largely compatible with the MIPS instruction set. The deal with Xemics, a Swiss company, combines a lower-end version of Massana's DSP (the FILU-50) with a proprietary 8-bit RISC microcontroller core (CoolRISC). [May 8, 2000]

• Figure 1: Block diagram of Massana's FILU-200 DSP mated to Lexra's LX4180 CPU.

Lexra has introduced its fifth MIPS-like embedded-processor core, the LX4189. It's very similar to the 32-bit LX4180 core rolled out a year ago, except that it has an additional pipeline stage to reach higher clock frequencies. Lexra says the LX4189 is better suited for next-generation 0.15-micron fabrication processes. [May 8, 2000]

• Table 1: Comparison of Lexra's LX4189, LX4180, LX4080, LX4280, LX5280, MIPS Technologies' MIP32 4K, and MIPS64 5K cores.

The EDN Embedded Microprocessor Benchmark Consortium (EEMBC) has released its long-awaited first benchmark results. MIPS-compatible processors dominated this round of benchmarking, with three MIPS licensees (IDT, NEC, and Toshiba) subjecting five different chips to EEMBC's rigorous tests. The x86 architecture was represented by two processors—AMD's K6-2 and National Semiconductor's Geode GX1. Other early birds were Infineon (TriCore TC10GP), Mitsubishi (M16C/62A), and STMicroelectronics (ST20C2). NEC also benchmarked its V832 (a 32-bit CPU based on a proprietary architecture), and Toshiba tested its TMP95FY64F (a proprietary 16-bit microcontroller). To put the results in perspective, MDR has derived its own unofficial "EEMBCmark" composite scores. [May 1, 2000]

• Table 1: The EEMBC 1.0 benchmarks consist of 46 tests divided into five application suites.

• Table 2: The raw numbers that EEMBC reports for the automotive/industrial benchmark suite.

• Figure 1: Bar chart of MDR's unofficial "EEMBCmark" scores based on the normalized geometric means of EEMBC's raw benchmark results in the automotive/industrial suite.

• Figure 2: An X-Y scatter-plot chart that shows how each processor's performance relates to clock frequency. One dotted line is the average performance trendline and the other dotted line represents a linear increase in performance with clock speed.

• Figure 3: An X-Y scatter-plot chart that uses only the FFT test results from EEMBC's automotive/industrial suite, with trend and frequency/performance lines.

• Figure 4: Bar chart of MDR's unofficial EEMBCmark scores from EEMBC's consumer-software benchmark results.

• Figure 5: X-Y scatter-plot chart of the five processors tested in EEMBC's consumer-software suite, with trend and frequency/performance lines.

• Figure 6: Bar chart of MDR's unofficial EEMBCmark scores from EEMBC's networking suite.

• Figure 7: X-Y scatter-plot chart of seven processors tested in EEMBC's networking suite, with trend and frequency/performance lines.

• Figure 8: Bar chart of MDR's unofficial EEMBCmark scores from EEMBC's office-automation suite.

• Figure 9: X-Y scatter-plot chart of five processors tested in EEMBC's office-automation suite, with trend and frequency/performance lines.

• Figure 10: Bar chart of MDR's unofficial EEMBCmark scores from EEMBC's telecommunications suite.

• Figure 11: X-Y scatter-plot chart of six processors test in EEMBC's telecommunications suite, with trend and frequency/performance lines.

PicoTurbo, a two-year-old startup based in Milpitas, Calif., has a new twist on ARM: a family of embedded-processor cores that's compatible with the ARM architecture. Indeed, the cores are apparently too compatible for ARM, which has filed a patent-infringement lawsuit against picoTurbo in U.S. District Court in San Jose. PicoTurbo maintains that its cores do not infringe on ARM's patents because they are based on an independently designed "clean room" microarchitecture. [April 17, 2000]

• Figure 1: Block diagram of the picoTurbo pT-110.

• Figure 2: Comparing the ARM9 and ARM10 pipelines with the picoTurbo pT-100, pT-110, and pT-120 pipelines.

• Table 1: Comparing features, performance, and power consumption of the ARM9, ARM10, pT-100, pT-110, and pT-120 cores at 0.25 and 0.18 microns.

• Table 2: List of ARMv5T and ARMv5TE instructions not supported by picoTurbo's ARMv4T-compatible cores.

Squeezing more life out of a four-year-old core, Quantum Effect Devices (QED) is producing a new version of its 64-bit MIPS-compatible RM7000 processor in a 0.18-micron process from TSMC (Taiwan Semiconductor Manufacturing Co.). The new RM7000A will run up to 50% faster while consuming 66% less power than its predecessor. QED will soon follow with the RM7000B, which uses 0.15-micron transistors on the same-size die, boosting clock frequencies to 500MHz. [April 3, 2000]

• Table 1: Feature comparison of the QED RM7000, RM7000A, RM7000B, RM5261, IDT RC64575, IDT RC5000, and NEC VR5432.

• ARC Cores Builds IP Library: ARC Cores has acquired two companies—VAutomation and Precise Software Technologies—that for the first time allow it to supply intellectual property in the form of peripheral hardware and software to licensees of its configurable CPU cores. [April 10, 2000]

• LSI Logic Adopts AMBA: LSI Logic has adopted the Advanced Microcontroller Bus Architecture (AMBA) as the standard interconnect for its CoreWare system-on-a-chip design services. The decision throws more weight behind AMBA's bid to become the defacto standard for on-chip buses. [April 10, 2000]

• MIPS Joins Forces With TSMC: MIPS Technologies has formed a partnership with TSMC (Taiwan Semiconductor Manufacturing Co.) to make prehardened versions of its soft embedded-processor cores. The deal gives customers the option of paying a design-use fee instead of the higher cost of a MIPS architectural license while saving the time and trouble of porting a soft core to an IC process themselves. [April 3, 2000]

While bytecode-native Java chips continue struggling to find a market, a team led by former Sun engineers has invented a novel alternative: a coprocessor that attaches to any CPU core and translates Java bytecodes into native instructions on the fly. The coprocessor is available now as a licensable Verilog model from JEDI Technologies, a Santa Clara-based startup founded in 1998. [March 27, 2000]

• Figure 1: Block diagram of the JSTAR instruction-path coprocessor.

• Figure 2: Embedded CaffeineMark 3.0 results for JSTAR.

• Sidebar: Java Chips Fight an Uphill Battle

Everything is bigger in Texas, including the DSPs. The Texas Instruments TMS320C62x-series DSP core, already the T. Rex of digital-signal processing, is about to be surpassed by an even more powerful beast. TI says its new TMS320C64x core offers about 10 times the performance of the existing core—plus greater code density and full compatibility with 'C62x software. TI isn't ignoring the opposite end of the market either. A second new core, the 'C55x, supplements the popular 'C54x and brings higher performance, lower power consumption, and greater code density to low-power DSPs. [March 6, 2000]

• Figure 1: Block diagram of the 'C64x DSP core.

• Figure 2: Internal resources of the eight function units in the 'C64x.

• Figure 3: The new 'C64x instruction format dramatically reduces NOPs.

• Figure 4: Block diagram of the 'C55x DSP core.

• Table 1: Several new instructions added to the 'C64x.

• Table 2: Comparison of TI's 'C64x, 'C62x, 'C67x, StarCore's SC140, and Analog Devices' ADSP-TS001 TigerSHARC DSP cores.

• Table 3: Several new instructions added to the 'C55x.

• Table 4: Comparison of TI's 'C55x, 'C54x, Lucent's DSP16000, Motorola's DSP56600, StarCore's SC140, and Analog Devices' ADSP-219x DSP cores.

• Another New DSP Core From TI: Texas Instruments has announced the TMS320C28x, its third new DSP core in less than a month. The 'C28x is designed for DSPs in the $10 range and extends TI's 'C2000 series of 16-bit fixed-point DSPs. [March 20, 2000]

• Motorola Buys C-Port: Smart Move: By offering $430 million in stock for C-Port, a fabless network-processor startup, Motorola is acquiring a powerful NPU to complement its existing lines of communications chips. At the same time, the deal counters some recent incursions onto Motorola's turf by major rivals such as IBM and Intel. [March 6, 2000]

A detailed 7,000-word analysis of Transmeta's Crusoe processors, which achieve x86 compatibility and low power consumption by running "code-morphing software" on efficient VLIW chips. This article examines Transmeta's unusual design approach, the LongRun voltage/frequency-scaling technology, the tradeoffs of emulation, the hardware support for emulation in the chips, and Transmeta's business strategy. [February 14, 2000]

• Figure 1: Block diagram of the Crusoe TM3120 processor.

• Figure 2: Block diagram of the Crusoe TM5400 processor.

• Figure 3: Crusoe's VLIW instruction formats.

• Figure 4: Crusoe's pipelines for ALU, floating-point, load/store, and branch instructions.

• Figure 5: Color die photo with floorplan overlay of the TM3120.

• Figure 6: Color die photo with floorplan overlay of the TM5400.

• Figure 7: How Transmeta's "code-morphing software" translates x86 instructions into native VLIW instructions.

To exploit the latest hot-product category—Internet gizmos—Hitachi has added an Ethernet interface and DSP instructions to one of its best-selling SuperH processors. The result is the new SH7615, which samples in March and is scheduled for volume production in June. Although in most ways the SH7615 is a relatively minor variation of Hitachi's existing SH7604 and SH7612 chips, it brings together the critical features of network connectivity and digital-signal processing for the first time in a SuperH processor. [January 24, 2000]

• Figure 1: Block diagram of Hitachi's SH7615.

• Table 1: Comparison of the SH7615 to Hitachi's SH7612, Infineon's Harrier-XT, IBM's PowerPC 405GP, Lexra's LX5280, ARM's ARM9E, and ARC Cores' ARC 3.

This detailed article reviews the embedded-processor market in 1999, focusing on major new trends, the most important new processors, and the most active semiconductor vendors. It also looks forward to the likely trends in 2000, predicting which companies, processors, and product categories will generate the most news in the coming year. In addition, we list the top seven embedded processors announced during the year and reveal our choice for the Best Embedded Processor of 1999. [January 17, 2000]

• Figure 1: Pie chart of 32/64-bit embedded-processor unit sales in 1999, broken down by CPU architecture.

• Figure 2: Price/performance comparison of four top embedded processors for mobile applications: Intel StrongARM SA-110, NEC VR4121, Hitachi SH7708, and Motorola DragonBall EZ.

• Sidebar: Key Embedded Events of 1999

• Sidebar: Best Embedded Processor 1999

• HP and ST Collaborate on VLIW: Hewlett-Packard Labs and STMicroelectronics have jointly developed a new customizable VLIW embedded-processor technology that will debut later this year. The technology allows developers to rapidly create application-specific VLIW processors with compatible development tools, simulators, and RTOS kernels. [January 24, 2000]

• Centillium Licenses MIPS32 4Kp Core: Centillium Communications has licensed the MIPS 4Kp core from MIPS Technologies for a new family of hybrid CPU/DSP processors scheduled for introduction in 2H00. The Fremont-based company plans to integrate the 4Kp with its own DSP core to create a system-on-a-chip (SOC) device for wired-communications products. [January 31, 2000]

• Motorola's Symphony Plays Digital Music: Motorola's latest DSP—the DSP56366 Symphony—has enough performance and on-chip memory to handle a wide variety of digital-audio standards, and it's aimed at the lucrative market for next-generation consumer-audio products. Sampling this quarter and scheduled for volume production in 2Q00, Symphony is a 24-bit fixed-point DSP that's compatible with Motorola's DSP56300 family. [January 31, 2000]

It took four years and two leaps in IC process technology, but NEC Electronics has finally announced a mobile embedded processor that appears to surpass the StrongArm's famed combination of performance and power consumption. NEC's new VR4122, scheduled for production in 2Q00, barely edges out StrongArm's MIPS/watt ratio, though not quite its stated performance. [December 27, 1999]

• Table 1: Comparison of the NEC VR4122 with the NEC VR4121, NEC VR4111, Intel SA-1110, Intel SA-2, and Hitachi SH7751.

• SiByte Licenses MIPS for Network Processor: More refugees from Digital Semiconductor have surfaced, and they're working on a MIPS-based network processor. Their Santa Clara-based startup, SiByte, recently licensed the MIPS64 instruction-set architecture from Mips Technologies.

• Motorola Releases Specs for On-Chip Bus: As it promised six months ago, Motorola's semiconductor products sector (http://mot-sps.com/) has released the specifications for its new core-independent on-chip peripheral bus, formerly known as IP Bus.

• Embedded Benchmarks Ready for Prime Time: EEMBC (EDN Embedded Microprocessor Benchmark Consortium) has released version 1.0 of two benchmarking suites: the automotive/industrial suite and the telecommunications suite.

Here's a detailed analysis of the patent-infringement lawsuit that Mips Technologies filed against Lexra in October, with emphasis on the technical foundations of Mips' allegations and Lexra's possible defense. The lawsuit focuses on two unusual features of the MIPS architecture: unaligned load/store instructions and SIMD instructions with extended-precision math. [December 6, 1999]

• Figure 1: How the MIPS unaligned load/store instructions work.

• Figure 2: The assembly code that Lexra uses to emulate unaligned load/store instructions.

• Figure 3: Block diagram of the dual MAC units in Lexra's LX5280 microprocessor core.

Jet-setters who want to stay in touch won't have to keep packing more cell phones than shoes much longer. Motorola's new DSP56690 is a highly integrated embedded processor that supports all of the most common wireless standards likely to be encountered on a globe-hopping journey. [December 6, 1999]

• Figure 1: Block diagram of the DSP56690.

• ADI's First TigerSharc DSP Has Sharp Teeth: In a bid to seize the lead in DSP performance, Analog Devices (ADI) has announced the ADSP-TS001, the first implementation of its much-delayed TigerSharc architecture.

• ADI, StarCore Offer Vitamin C for DSPs: This week, two DSP vendors released preliminary benchmarks of alpha- or beta-version compilers for preproduction DSPs. Analog Devices (ADI) and StarCore claim their C compilers can achieve a significant amount of the performance normally associated with hand-coded assembly language. ADI's compiler is for the TigerSharc ADSP-TS001, and StarCore's compiler is for the SC140.

• Embedded Processor Forum Moved to June: Embedded Processor Forum, sponsored by Cahners MicroDesign Resources, will be held June 12-16 instead of in May as previously announced.

Cirrus Logic's new EP7212 Maverick chip is an application-specific standard product (ASSP) for mobile information appliances that need digital-audio capabilities. Cirrus is aiming Maverick at next-generation products that can download and play audio files from the Internet, in addition to performing the more common tasks expected of handheld computers. [November 15, 1999]

• Figure 1: Projected sales of portable Internet-audio players.

• Figure 2: EP7212 Maverick block diagram.

• Table 1: Comparison of Cirrus Logic's EP7212, EP7211, and EP7209 chips.

• Intel Bids $1.6 Billion for DSP Communications: Intel is buying DSP Communications, a supplier of chip sets and software to cell-phone manufacturers, as the latest in a series of acquisitions in the communications and networking industries.

• Motorola's DragonBall Rolls Faster: The new DragonBall 68VZ328 processor is an improvement over existing DragonBall chips—both the 68328 in the original PalmPilot and the 68EZ328 in new models from 3Com and startup Handspring. The DragonBall VZ doubles the clock frequency to 33 MHz, adds color capability to the integrated LCD controller, and has other enhancements.
  • Table: Comparison of the DragonBall 68328, 68EZ328, and 68VZ328.

• Arm Extends Reach of ARM10 Pipeline: Unable to attain its frequency goals with the original five-stage pipeline, Arm has extended the ARM10's pipeline to six stages. Arm recently taped out the new core and plans to make it available to licensees on schedule in 2Q00.
  • Figure: Pipeline diagram comparing the ARM9 and old ARM10 pipeline with the new ARM10.

• Zoran's Soft DSP Core Optimized for Audio: Zoran has announced Muzichord, a new synthesizable DSP core for audio applications. The 32-bit fixed-point DSP has enough speed and precision to handle next-generation audio standards such as DVD audio.

• Mips Technologies Sues Lexra Over Patents: Although Mips Technologies and Lexra settled a lawsuit last year over trademark issues and product claims, it seems their legal battles aren't over. Mips has filed another lawsuit against Lexra, this time alleging patent infringement in the design of Lexra's synthesizable processor cores, which are mostly compatible with the MIPS architecture.

IBM's new PowerPC 440 core is the first officially announced embedded-processor core that's projected to hit 1,000 Dhrystone MIPS. It achieves some other firsts as well. It's the first core to implement Book E, the new embedded PowerPC architecture defined by IBM and Motorola. And it's the first core to use a 128-bit version of IBM's on-chip CoreConnect bus. [October 25, 1999]

• Figure 1: PowerPC 440 block diagram.

• Table 1: A comparison of recently announced high-performance embedded cores, including the PowerPC 440, Mips 5Kc, IDT RISCore 64600, Intel StrongArm-2, and Hitachi/STMicroelectronics SH-8000/ST50.

Mips Technologies is getting softer all the time, but that's not good news for competitors. Mips has announced the first implementation of its MIPS64 instruction-set architecture—and the first 64-bit soft core from any microprocessor vendor. It joins a growing line of synthesizable embedded cores from Mips, including the MIPS32 4Kc, 4Kp, and 4Km. [October 25, 1999]

• Figure 1: MIPS64 5Kc pipeline diagram.

• Figure 2: MIPS64 5Kc block diagram.

• Massana's DSP Coprocessor Bolts Onto CPUs: While many embedded-processor vendors are adding DSP extensions, Massana's FILU-200 is quite different: it's a synthesizable DSP coprocessor that attaches to the CPU's memory bus and is programmable with C function libraries.

• ADI Adopts AMBA for New DSPs: Analog Devices has unveiled a new DSP core, the ADSP-219x, and has announced that it will use Arm's Advanced High-Performance Bus (AHB) interface, which is part of the open-standard Advanced Microcontroller Bus Architecture (AMBA).

Hitachi and STMicroelectronics have collaborated on a new 64-bit embedded processor architecture called SH-5 that preserves backward compatibility with existing SuperH software. It's a clever combination of power and efficiency that keeps Hitachi and ST in the accelerating race against other high-performance embedded processors, such as those based on PowerPC, MIPS, and StrongArm cores. [October 6, 1999]

• Table 1: The complete SH-5 instruction set.

• Figure 1: Block diagram of the first SH-5 core.

• Figure 2: A comparison of the new SH-5 and existing SuperH instruction formats.

• Figure 3: Existing SuperH registers are mapped onto the new, larger SH-5 register file.

• Figure 4: Block diagram of the first SH-5 system on a chip, which Hitachi calls the SH8000 and ST calls the ST50.

The new MSC8101 is the first digital-signal processor (DSP) to emerge from the StarCore alliance between Motorola and Lucent. It's so network oriented that Motorola has considering inventing a new buzzword for it: NetDSP. [October 6, 1999]

• Figure 1: Block diagram of the Motorola MSC8101.

• IBM, C-Port Network Processors Challenge Intel: At about the same time as Intel's IXP1200 announcement, C-Port and IBM Microelectronics separately announced two network processors aimed at the same market—high-speed routers and related communications equipment.

• Triscend Ships First Reconfigurable 8051: The first member of Triscend's E5 family—the 8051-based TE520—is now in full production, with additional members to follow next year. It combines an 8051 processor core with reprogrammable logic.

• MIPS32 4Km Core Has Fast MAC: Mips Technologies' new 4Km is the third synthesizable core to adopt the MIPS32 instruction-set architecture introduced earlier this year for embedded applications. The 4Km combines features of the 4Kc and 4Kp cores, which were announced in May.
  • Table 1: Feature comparison of the MIPS32 4Kc, 4Kp, and 4Km cores.

Only Intel could have this kind of luck: it gets sued by Digital Semiconductor for patent infringement, ends up acquiring its foe after an out-of-court settlement, gains a billion-dollar fab and a StrongArm license in the deal, and then discovers that it has also inherited a groundbreaking network processor that was secretly under development. Perhaps Intel should encourage competitors to file lawsuits more often. [September 13, 1999]

• Sidebar: An Architecture for Networking

• Figure 1: IXP1200 block diagram.

• Figure 2: The IXP1200's die is 126mm^2 in a 0.28-micron process.

• Figure 3: Each microengine has 256 registers in separate files and banks.

• Table 1: The complete IXP1200 microengine instruction set.

• IDT Unveils New 64600 Core: IDT is augmenting its line of MIPS-compatible processors with a third 64-bit core designed for high-performance embedded applications: the RISCore 64600.

• AMD Teaches Old Core New Tricks: AMD has announced the Elan SC520, the first in a new series of its x86-based processors for embedded applications.

If there were any doubts that VLIW has succeeded RISC as the most important influence on new microprocessor architectures, they vanished this month when Sun pulled the latest example out of its hat: MAJC (pronounced "magic"), the Microprocessor Architecture for Java Computing. It's a Java-friendly (though not Java-specific) architecture that's particularly amenable to multithreading and chip multiprocessing (CMP)—the integration of multiple CPU cores on a single die. [August 23, 1999]

• Figure 1: The format of MAJC's VLIW instruction packets.

• Figure 2: Vertical multithreading switches contexts among program threads during memory accesses.

• Figure 3: VLIW packet processing in a four-way MAJC processor with orthogonal function units.

• Figure 4: MAJC's unified register file.

Broadening its range of 64-bit embedded processors, IDT is sampling two new MIPS-compatible chips based on the high-performance RC5000 core. The new RC64574 and '575 extend that core in many of the same ways that IDT's RC64474 and '475 extended the 64-bit RC4700 core last year. [August 23, 1999]

• Table 1: Comparing IDT's new processors with existing IDT processors and other MIPS-compatible chips from QED and NEC.

• Mips Adds a New Dimension to MIPS64: Mips Technologies has introduced MIPS-3D, a set of 13 instructions for MIPS64 embedded processors.

• Arm Announces Two Soft Cores With DSP: Arm has unveiled two synthesizable cores based on the ARM9E announced at Embedded Processor Forum last spring. Both include the ARM9E's digital-signal processing (DSP) extensions.

Alliance Semiconductor's new IPRP-V4 (Internet Protocol Routing Processor) architecture certainly defies classification. Is it embedded-memory logic or embedded-logic memory? Either way, it's designed to solve a growing problem: managing and searching IP forwarding tables to keep up with high-end routers and fiber-optic backbones. [August 2, 1999]

• Figure 1: IPRP-V4 block diagram.

• Table 1: IPRP-V4 instruction set.

Battered but not beaten by its brief foray onto Intel's turf, National Semiconductor is launching a long-anticipated flank attack—an "information appliance on a chip" designed for non-PC devices in homes and offices. The highly integrated chip, scheduled for delivery next January, is the key to National's post-PC strategy. And it's probably the last chance for National to salvage any value from its costly rental of Cyrix. [August 2, 1999]

• Figure 1: Geode SC1400 block diagram.

Fujitsu Microelectronics has announced a new embedded-processor architecture that's definitely buzzword compliant. It has very long instruction words (VLIW), multimedia instructions, digital-signal-processing (DSP) features, a customer-extensible instruction set, and configurable cores. And the cores are designed to be combined with macro libraries to build system-on-a-chip (SOC) parts for consumer electronics, automotive-navigation computers, and communications devices. [August 2, 1999]

• Figure 1: Fujitsu's FR-V architecture consists of five instruction subsets that customers may combine and customize in different ways.

• LX4280 Fills Lexra's Midrange: Lexra has announced a MIPS-compatible processor core that it claims will be the fastest such 32-bit core on the market. The new LX4280 is expected to deliver 275 Dhrystone MIPS at a worst-case clock frequency of 200 MHz. At its maximum estimated frequency of 266 MHz, the LX4280 should deliver at least 350 MIPS.

IBM's latest PowerPC processor, the 405GP, is a highly integrated system on a chip (SOC) with PCI, Ethernet, an SDRAM controller, and the first implementation of CodePack code compression. What's potentially more important is that IBM is using the 405GP to kick off the CoreConnect bus—an on-chip bus architecture for SOCs that IBM is offering free to all comers. [July 12, 1999]

• Figure 1: The CoreConnect architecture consists of three buses: the high-speed processor local bus, the lower-speed on-chip peripheral bus, and the device-control-register bus.

• Figure 2: Block diagram of IBM's PowerPC 405GP.

Microprocessors without multimedia extensions are becoming as rare as unemployed engineers in Silicon Valley. Equally rare are embedded-processor companies that don't have a system on a chip and "post-PC" strategy. One of the latest companies to swell the tide is SandCraft, which is introducing a new MIPS-compatible embedded CPU core with digital-signal-processing (DSP) and single-instruction, multiple-data (SIMD) extensions. [July 12, 1999]

• Figure 1: Block diagram of the SandCraft SR1-GX.

• Figure 2: SandCraft's conception of a system on a chip for a next-generation set-top box (block diagram).

• Mips and Chartered Form Unique Partnership: Mips Technologies and Chartered Semiconductor have formed a new partnership that allows customers to use Mips's latest CPU cores without negotiating a special MIPS license or porting the soft cores to an IC process.

• Motorola Plugs PowerQuicc Gap: The new PowerQuicc MPC855T fills a price and features gap in the PowerQuicc line between the six-member MPC850 family and the eight-member MPC860 family.

After years of searching for an alternative to Dhrystone and other marginally useful benchmarks, the industry finally has a way to compare the performance of microcontrollers, microprocessors, compilers, and other system components. It's a series of benchmarking suites from EEMBC (pronounced "embassy"), the EDN Embedded Benchmark Consortium. EEMBC has been working on its benchmarking methods for almost three years. [June 21, 1999]

• The Usual Suspects: A list of all 29 EEMBC board members and how much it costs to join EEMBC.

• Figure 1: Geometric means are one way to derive composite scores from the EEMBC data, but the results may be misleading.

• Table 1: Preliminary raw scores from the EEMBC automotive/industrial suite.

• Table 2: The complete list of benchmark tests in the five categories of the EEMBC suites (version 0.9).

Hitachi's new SuperH 7751 joins the exclusive club of embedded processors that have an integrated PCI interface. It also runs Microsoft's Windows CE and consumes less than half a watt of power, opening up new possibilities for mobile CE-based devices that could make use of PCI connectivity. [June 21, 1999]

• Figure 1: Block diagram of the SH7751.

• Intel Expands Embedded x86 Lineup: Two Pentium II chips in surface-mount BGA packages and a pair of Pentium II embedded modules.

• Motorola Enhances PowerPC Line: The PowerPC 745 and PowerPC 755 improve on the existing PowerPC 740 and PowerPC 750.

MIPS Technologies has unveiled two new architectures that will carry the Rx000 family toward the future of high-performance embedded cores and system-on-a-chip devices. The new architectures, known as MIPS32 and MIPS64, are 32- and 64-bit derivatives of existing MIPS architectures. The company also announced the first two cores based on MIPS32: the 4Kc and the 4Kp, popularly known as Jade and Jade Lite. [May 31, 1999]

• Table 1: New instructions in the MIPS32 architecture.

• Figure 1: Block diagram of the Jade/4K soft core.

• Figure 2: The original R3000 execution pipeline.

• Figure 3: The Jade execution pipeline.

Like Texas Instruments and Analog Devices, the Motorola-Lucent alliance known as StarCore is betting on the Great Wide Hope: VLIW. StarCore's new SC140 is the third recent DSP architecture to apply long instruction words and a wide-issue core to the challenge of delivering more instruction-level parallelism. [May 10, 1999]

• Table 1: Comparison of the StarCore SC140, TI 'C6202, and Analog Devices TigerSharc DSPs.

• Table 2: Key operations in the SC140 instruction set.

• Figure 1: Block diagram of the SC140 core.

Reaffirming its commitment to the StrongArm architecture cast off by Digital, Intel is introducing a new integrated microprocessor with a companion chip. The new SA-1110 and SA-1111 will strengthen StrongArm's position in the market for highly integrated power-miserly processors. Intel plans to deliver the new chips in 3Q99. [April 19, 1999]  

As if "write once, run anywhere" weren't an ambitious enough target, Sun is now aiming for "write once, run everywhere." Sun's new Java-based Jini technology tries to make it easier for IT administrators and befuddled users to add hardware devices and software services to networks. "Plug and work, not plug and play" is the new mantra. [March 29, 1999]

• Figure 1: Jini services use remote method invocations to interact over networks.

• Figure 2: Jini services can be provided by hardware devices or by programs written in Java or native code.

• Figure 3: Microsoft's Universal Plug and Play relies on standardized service protocols (such as LPR) instead of Java interfaces.

The recent Microprocessor Forum included a highly anticipated demonstration of Jawa 3.0 and a new interface for electronic musical instruments called Jimi. Jawa now offers numerous enhancements over earlier versions, including more efficient garbage collection, scrap collection, tighter security bolts, and vital bug fixes for the dynamic compiler. [April Fool's Day Wrapper: March 29, 1999]

Never mind RISC and CISC. "NISC" and "WISC" are some of the fanciful terms suggested for a unique embedded processor from Sweden that has rewritable microcode, microcode-level concurrency, native Java bytecode execution, multiple register banks, and other unusual features. [December 28, 1998]

• Table 1: Comparison of the GP1000 and Sun's MicroJava 701.

• Figure 1: Block diagram of the GP1000.

• Figure 2: GP1000 die photo with floorplan overlay.

• Figure 3: Eight register banks allow the GP1000 to switch among concurrent processes without saving or restoring registers.